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Strobel M.,Institute For Mikroelektronik Stuttgart Ims Chips | Dottling D.,Pilz GmbH and Co. KG
Advanced Optical Technologies | Year: 2013

The first part of this paper describes the high dynamic range CMOS (HDRC®) imager - a special type of CMOS image sensor with logarithmic response. The powerful property of a high dynamic range (HDR) image acquisition is detailed by mathematical definition and measurement of the optoelectronic conversion function (OECF) of two different HDRC imagers. Specific sensor parameters will be discussed including the pixel design for the global shutter readout. The second part will give an outline on the applications and requirements of cameras for industrial safety. Equipped with HDRC global shutter sensors SafetyEYE® is a high-performance stereo camera system for safe three-dimensional zone monitoring enabling new and more flexible solutions compared to existing safety guards. © 2013 Thoss Media & De Gruyter.


Kaschel M.,Institute For Mikroelektronik Stuttgart Ims Chips | Letzkus F.,Institute For Mikroelektronik Stuttgart Ims Chips | Butschke J.,Institute For Mikroelektronik Stuttgart Ims Chips | Skwierawski P.,Karlsruhe Institute of Technology | And 2 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2016

We present the technology steps to integrate an Echelle grating in the process flow of silicon-organic hybrid (SOH) modulators or related active devices. The CMOS-compatible process flow on SOI substrates uses a mix of optical i-line lithography and electron beam lithography (EBL). High speed optical data communication depends on wavelength divisions multiplexing and de-multiplexing devices like Echelle gratings. The minimum feature sizes vary from device to device and reach down to 60 nm inside a modulator, while the total area of a single Echelle grating is up to several mm2 of unprocessed silicon. Resist patterning using a variable shape beam electron beam pattern generator allows high resolution. An oxide hard mask is deposited, patterns are structured threefold by EBL and are later transferred to the silicon. We demonstrate a 9-channel multiplexer featuring a 2 dB on-chip loss and an adjacent channel crosstalk better than -22 dB. Additionally a 45-channel Echelle multiplexer is presented with 5 dB on chip loss and a channel crosstalk better than -12 dB. The devices cover an on-chip area of only 0.08 mm2 and 0.5 mm2 with a wavelength spacing of 10.5 nm and 2.0 nm, respectively. © 2016 SPIE.


Harendt C.,Institute For Mikroelektronik Stuttgart Ims Chips | Yu Z.,Institute For Mikroelektronik Stuttgart Ims Chips | Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims Chips | Kostelnik J.,Wurth Elektronik GmbH and Co. KG | And 2 more authors.
European Solid-State Device Research Conference | Year: 2014

Electronics embedded in foil is an enabling technology for flexible electronics and for special form factors of electronic components. In contrast to strictly printed electronics, Hybrid Systems-in-Foil (HySiF), comprising thin flexible, embedded chips and large-area thin-film electronic elements, feature a versatile and reliable technological solution for industrial applications of flexible electronics. This paper provides a comprehensive overview of HySiF technology, including aspects of thin-chip fabrication, reliability and assembly. Also presented is an industrial demonstrator utilizing such a HySiF component. © 2014 IEEE.


Kohler H.,BIAS Bremen Institute of Applied Beam Technology | Jayaraman V.,BIAS Bremen Institute of Applied Beam Technology | Brosch D.,Institute For Mikroelektronik Stuttgart Ims Chips | Hutter F.X.,Institute For Mikroelektronik Stuttgart Ims Chips | Seefeld T.,BIAS Bremen Institute of Applied Beam Technology
Physics Procedia | Year: 2013

In materials processing heat input into parts is a major issue. To reduce heat impact, temperatures can be evaluated to optimize processes i.e. for low distortion, low dilution or small heat affected zones. For the first time a new sensor which combines ratio pyrometry with 2D-resolved measurement is applied for laser processing. The advantages of independence of emissivity and attenuation of the thermal radiation together with 2D-temperature information are demonstrated on laser cladding. The temperature distribution at the parts' surfaces becomes available with quantitatively high precision. This information was successfully applied to validate FEM-based temperature field simulations. © 2013 The Authors.


Ferwana S.,Institute For Mikroelektronik Stuttgart Ims Chips | Keck J.,Hahn Schickard | Hassan M.-U.,Institute For Mikroelektronik Stuttgart Ims Chips | Harendt C.,Institute For Mikroelektronik Stuttgart Ims Chips | Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims Chips
20th European Microelectronics and Packaging Conference and Exhibition: Enabling Technologies for a Better Life and Future, EMPC 2015 | Year: 2015

The filling process of Through-Silicon Via (TSV) based on printed silver using the Aerosol Jet™ method is presented and discussed. TSVs with different diameters as via-last process in 18 μm ultra-Thin ChipFilm™ dies, including a self-Aligned etching process and their passivation are demonstrated. Daisy chain test structures on top of ChipFilm™ dies and on the bottom wafer are used for demonstration purposes. Moreover, the successful 3D-integration of an 18 μm ChipFilm™ die on the wafer using patterned photosensitive BCBs including a plasma treatment step right before stacking is presented. Finally, the work is concluded by demonstrating the results of electrical characterization of the filled and annealed TSVs at 180°C. © 2015 IMAPS Europe.


Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims Chips | Appel W.,Institute For Mikroelektronik Stuttgart Ims Chips | Harendt C.,Institute For Mikroelektronik Stuttgart Ims Chips | Rempp H.,Institute For Mikroelektronik Stuttgart Ims Chips | And 2 more authors.
Solid-State Electronics | Year: 2010

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies. © 2010 Elsevier Ltd.


Utermohlen F.,Robert Bosch GmbH | Herrmann I.,Robert Bosch GmbH | Etter D.B.,Institute For Mikroelektronik Stuttgart Ims Chips | Sun S.H.,Institute For Mikroelektronik Stuttgart Ims Chips | Burghartz J.,Institute For Mikroelektronik Stuttgart Ims Chips
2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 | Year: 2013

A model for the electrical behavior of pn-junction diodes biased in forward direction and used as a temperature sensitive device (TSD) in microbolometers is presented. It is based on the well-known Shockley equation extended by the ideality factor m. We demonstrate that the largest temperature sensitivity can be reached for diodes at low current density operation featuring a high ideality factor m > 1. © 2013 IEEE.


Utermohlen F.,Robert Bosch GmbH | Herrmann I.,Robert Bosch GmbH | Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims Chips
Smart Systems Integration 2015 - 9th International Conference and Exhibition on Integration Issues of Miniaturized Systems: MEMS, NEMS, ICs and Electronic Components, SSI 2015 | Year: 2015

Due to their room temperature operation, the CMOS compatible manufacturing process and the ambitious scaling effort in MEMS technology within the last years, MEMS microbolometers are excellent candidates for low-cost thermal imaging systems which can be used for automotive as well as for consumer applications. Since the application specific sensor requirements with regard to performance, robustness, resolution and cost are very diverse, a lean and fast development without a time-consuming manufacturing of several prototypes becomes indispensable. Therefore, a physics-based scalable compact model covering the full signal path from the IR emission by an object to the evaluation circuit has been developed and experimentally validated.


Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims Chips | Ferwana S.,Institute For Mikroelektronik Stuttgart Ims Chips | Harendt C.,Institute For Mikroelektronik Stuttgart Ims Chips
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 | Year: 2015

Ultrathin chip fabrication is an enabler of high-performance hybrid systems-in-foil (HySiF) for flexible electronics as well as 3D IC's. Minimum chip thickness, exact thickness control, uniformity and reproducibility as well as smoothness of chip surfaces and edges are important requirements in both applications. Most commonly, thinning is arranged at wafer level prior to chip singulation, which is classified as a subtractive method. In contrast, an additive thin-chip technology called ChipFilm™ is presented here, meeting all those requirements. It is shown that by using ChipFilm™ both wafer-level and chip-level thinning are feasible. © 2015 IEEE.


Strobel M.,Institute For Mikroelektronik Stuttgart Ims Chips
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2012

Logarithmic High Dynamic Range CMOS (HDRC) image sensors exhibit the highest Dynamic Range and a straight forward image acquisition compared to other High Dynamic Range imagers or techniques. The nearly constant pixel random noise over the illumination range, in contrast to sensors with linear or piece-wise linear Opto Electronic Conversion Function (OECF), gives rise to a balanced contrast resolution. The Noise Equivalent Contrast (NEC) will be introduced as a figure of merit to compare both imager types with nonlinear and linear OECF, which leads to the incremental Signal-to-Noise Ratio (iSNR) and SNR, respectively. This will be shown by measurements of OECF and NEC performed with a logarithmic HDRC imager. The resulting iSNR, related to ISO15739, will be quantitatively compared to SNR data of a linear imager according to EMVA1288 standard. The benefits of the logarithmic imager come with the necessity to correct CMOS technology dependent pixel to pixel variations, namely the MOS transistor threshold and gain variations and the photodiode dark current distribution contributing to an overlaid Fixed Pattern in the raw image data. Depending on the required quality and the allowed computational complexity a Fixed Pattern Correction (FPC) algorithm should correct from the most dominant up to all three non-uniformity parameters per pixel in the digital signal chain of a camera. © 2012 SPIE.

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