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Stuttgart Mühlhausen, Germany

Asif A.,University of Stuttgart | Richter H.,Institute For Mikroelektronik Stuttgart Ims | Burghartz J.N.,University of Stuttgart | Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims
IEEE - 2011 Semiconductor Conference Dresden: Technology, Design, Packaging, Simulation and Test, SCD 2011 - International Conference, Workshop and Table-Top Exhibition | Year: 2011

Video streaming and fast processing in System-in-Foil (SiF) applications require high performance and ultra-thin (< 20 μm), high-voltage transistors on foil. Chipfilm™ technology offers an efficient way of precisely defining the thickness of ultra-thin chips. An ultra-thin (< 20 μm) single-crystal silicon N-LDMOS transistor is realized for Chipfilm™ technology. The device has a breakdown voltage (V br) of more than 100 volts. With an I on/I off ratio of >10 6, the drain current (I d) is ∼ 4 mA for channel width (W) = 50 μm and channel length (L) = 10 μm. The process flow is fully compatible with conventional high-voltage CMOS process. © 2011 IEEE.

Wacker N.,Institute For Mikroelektronik Stuttgart Ims | Richter H.,Institute For Mikroelektronik Stuttgart Ims | Hassan M.-U.,Institute For Mikroelektronik Stuttgart Ims | Rempp H.,Institute For Mikroelektronik Stuttgart Ims | Burghartz J.N.,Institute For Mikroelektronik Stuttgart Ims
Solid-State Electronics | Year: 2011

This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes. © 2010 Elsevier Ltd. All rights reserved.

Wacker N.,Institute For Mikroelektronik Stuttgart Ims | Richter H.,Institute For Mikroelektronik Stuttgart Ims | Hoang T.,Institute For Mikroelektronik Stuttgart Ims | Gazdzicki P.,German Aerospace Center | And 4 more authors.
Semiconductor Science and Technology | Year: 2014

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ≤20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chip's edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure. © 2014 IOP Publishing Ltd.

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