Institute for Microelectronics Stuttgart IMS CHIPS

Stuttgart, Germany

Institute for Microelectronics Stuttgart IMS CHIPS

Stuttgart, Germany
SEARCH FILTERS
Time filter
Source Type

Zaki T.,Institute For Microelectron Stuttgart Ims Chips | Zaki T.,University of Stuttgart | Ante F.,Max Planck Institute for Solid State Research | Zschieschang U.,Max Planck Institute for Solid State Research | And 6 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and consumes an area of 2.6× 4.6 mm2. The converter has a maximum update rate of 100 kS/s and a maximum output voltage swing of 2 V. The measured DNL and INL at an update rate of 1 kS/s are - 0.69 and 1.16 LSB, respectively. A spurious-free dynamic range (SFDR) of 32 dB has been measured for output sinusoids at 31 Hz (update rate of 1 kS/s) and 3.1 kHz (update rate of 100 kS/s). © 1966-2012 IEEE.


Endler S.,Institute for Microelectronics Stuttgart IMS CHIPS | Rempp H.,Institute for Microelectronics Stuttgart IMS CHIPS | Harendt C.,Institute for Microelectronics Stuttgart IMS CHIPS | Burghartz J.N.,Institute for Microelectronics Stuttgart IMS CHIPS
European Solid-State Device Research Conference | Year: 2011

A novel method in minimizing mechanical bending stress on CMOS devices in ultra-thin chips is presented. It is shown, that the stress due to thin chip bending is reduced by glue-attaching a bare silicon chip on top of the active chip, thus shifting the neutral line to the active layer. The effect of the top chip thickness is investigated experimentally, determining the optimum thickness value for stress compensation. Apart from this, an analytical model is used to calculate the stress in the active area of the CMOS devices in case of a stacked flexible system. This model is confirmed by experimental results. It is verified, that the viscoelastic behavior of the glue layer has little impact. Nevertheless, the homogeneity and the quality of the layer affect the stress compensation considerably. © 2011 IEEE.


Rodel R.,Max Planck Institute for Solid State Research | Letzkus F.,Institute for Microelectronics Stuttgart IMS CHIPS | Zaki T.,Institute for Microelectronics Stuttgart IMS CHIPS | Zaki T.,University of Stuttgart | And 7 more authors.
Applied Physics Letters | Year: 2013

Air-stable bottom-gate, top-contact n-channel organic transistors based on a naphthalene diimide exhibiting electron mobilities up to 0.8 cm2/Vs at low voltages were fabricated. Transistors with channel lengths of 1 μm show a transconductance of 60 mS/m, but are significantly limited by the contact resistance. Transmission line measurements in combination with contact resistance models were applied to investigate this influence. Both contact resistance and contact resistivity are proportional to the inverse gate overdrive voltage. Organic complementary ring oscillators were fabricated on a flexible plastic substrate showing record signal delays down to 17 μs at a supply voltage of 2.6 V. © 2013 AIP Publishing LLC.


Nawito M.,Institute for Microelectronics Stuttgart IMS CHIPS | Richter H.,Institute for Microelectronics Stuttgart IMS CHIPS | Burghartz J.N.,Institute for Microelectronics Stuttgart IMS CHIPS
2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015 | Year: 2015

This work presents a compact wide-range fully integrated sinusoidal signal generator for in vivo Electrochemical Impedance Spectroscopy applications. The circuit is based on a novel architecture combining aspects of direct digital synthesis and interpolation digital to analog conversion. The signal generator demonstrates very precise frequency tuning and high spectral purity, while offering a simple architecture and an uncomplicated clocking scheme. The circuit is fabricated using a 0.5μm sea of transistors CMOS process and occupies 0.32mm2 of active die area. Consuming 110μA at a 3V supply, the circuit covers eight decades of frequency from 1mHz to 100kHz and meets the necessary low energy and high precision requirements for implantable bio-diagnostics. © 2015 IEEE.


Zaki T.,University of Stuttgart | Zaki T.,Institute for Microelectronics Stuttgart IMS CHIPS | Rodel R.,Max Planck Institute for Solid State Research | Letzkus F.,Institute for Microelectronics Stuttgart IMS CHIPS | And 5 more authors.
Organic Electronics: physics, materials, applications | Year: 2013

This paper presents S-parameter characterization and a corresponding physics-based small-signal equivalent circuit for organic thin-film transistors (OTFTs). Furthermore, the impact of misalignment between the source/drain contacts and the patterned gate on the dynamic TFT performance is explored and a simple method to estimate the misalignment from the measured S-parameters is proposed. An excellent fit between theoretical and experimental S-parameters is demonstrated. For this study, OTFTs based on the air-stable organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) having a channel length of 1 μm and a gate-to-contact overlap of 5 or 20 μm and being operated at a supply voltage of 3 V are utilized. The intentional asymmetry between gate-to-source and gate-to-drain overlaps is precisely controlled by the use of high-resolution silicon stencil masks.© 2013 Elsevier B.V. All rights reserved.


Zhang Y.,Institute for Microelectronics Stuttgart IMS CHIPS | Zhang Y.,Intel Corporation | Scherjon C.,Institute for Microelectronics Stuttgart IMS CHIPS | Burghartz J.N.,Institute for Microelectronics Stuttgart IMS CHIPS | Burghartz J.N.,University of Stuttgart
IEEE Transactions on Industrial Electronics | Year: 2015

Due to high functional variety, wide power rating range, and relatively low product volumes, electronic systems for industrial application are difficult to economically be integrated on a chip. This paper presents the smart power gate array (SPGA), a novel application-specific integrated circuit (ASIC) platform exactly aimed at enabling cost-efficient single-chip integration of industrial electronic systems. The SPGA combines a low-voltage mixed-signal gate array with a structured high-voltage smart-power core, allowing for single-chip integration of signal conditioning, data processing, power management, actuator driving, and line communication functionalities required for industrial applications. Simultaneously, it offers low nonrecurring engineering cost and high design flexibility owning to the utilized gate array technology. In this paper, the SPGA concept is introduced to overcome integration limitations of existing ASIC technologies. Then, design and capabilities of the SPGA functional modules are described. Finally, a practical SPGA application example of single-chip integrated solenoid valve control and monitoring system is demonstrated. © 1982-2012 IEEE.


Zaki T.,Institute for Microelectronics Stuttgart IMS CHIPS | Zaki T.,University of Stuttgart | Ante F.,Max Planck Institute for Solid State Research | Zschieschang U.,Max Planck Institute for Solid State Research | And 6 more authors.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference | Year: 2011

Organic thin-film transistors (OTFT) processed at low-temperatures offer prospects for a vast number of integrated circuit applications in mechanically flexible, inexpensive, large-area and biomedical electronics [1]. In addition, the low-voltage operation capability of recent OTFTs makes them well-suited for battery-powered or radio frequency-coupled portable devices [2]. In such applications, data conversion to interface the digital processors with the analog world is an essential necessity. Here, we demonstrate a compact 6b current-steering D/A converter (DAC) circuit, built in OTFT technology, which is 1000x faster and 30x smaller than the previously published data for a 6b DAC [3]. These considerable improvements result from an OTFT fabrication process based on silicon stencil masks that provide submicron channel length capability and excellent transistor matching [4], [5]. © 2011 IEEE.


Endler S.,Institute for Microelectronics Stuttgart IMS CHIPS | Ferwana S.,Institute for Microelectronics Stuttgart IMS CHIPS | Rempp H.,Institute for Microelectronics Stuttgart IMS CHIPS | Harendt C.,Institute for Microelectronics Stuttgart IMS CHIPS | Burghartz J.N.,Institute for Microelectronics Stuttgart IMS CHIPS
IEEE Electron Device Letters | Year: 2012

A new concept for mechanically flexible stress and flex sensors is presented. A stack of two ultrathin chips is exploited to compensate both thermal effects and the vertical piezoresistive effect. By tailoring the thickness of the top die, the active devices of the bottom chip become stress compensated, whereas the devices of the top chip receive maximum stress. The structural arrangement enforces that the apparent vertical stresses and the temperatures of both dies are basically identical. Thus, the differential signal of both dies provides a temperature-compensated information about the 2-D stress and flexure. © 2012 IEEE.


Endler S.,Institute for Microelectronics Stuttgart IMS Chips | Rempp H.,Institute for Microelectronics Stuttgart IMS Chips | Harendt C.,Institute for Microelectronics Stuttgart IMS Chips | Burghartz J.N.,Institute for Microelectronics Stuttgart IMS Chips
Solid-State Electronics | Year: 2012

A new concept for compensating mechanical stress on CMOS devices in ultrathin chips is demonstrated. By glue-attaching a bare silicon chip on top of an active CMOS chip the neutral line of the entire flexible system is forced to match the active layer, thus reducing the mechanical bending stress on the CMOS devices. The optimum thickness of the top chip for perfect stress compensation is determined analytically and confirmed by experimental results. Moreover, the effect of the intermediate adhesive layer on the level of compensation is investigated. It is shown, that the viscoelastic behaviour of the glue layer is indeed negligible, but the layer thickness has to be controlled accurately. Finally, the mechanical stability of the stacked flexible system is characterized and compared to the strength of the uncompensated single-chip. Due to the considerably higher mechanical stability of the bare top chip the maximum curvature of the chip-stack is even higher compared to the single CMOS chip. © 2012 Elsevier Ltd. All rights reserved.


Yan H.,Technical University of Delft | MacIas-Montero J.G.,Technical University of Delft | Akhnoukh A.,Technical University of Delft | De Vreede L.C.N.,Technical University of Delft | And 2 more authors.
IEEE Transactions on Microwave Theory and Techniques | Year: 2011

Two highly integrated ultra-low-power binary phase-shift keying (BPSK) receivers for short-range wireless communications are presented. The receivers consist of a power divider, two injection-locked RC oscillators with limiting buffers, and an xor output stage. The demodulation principle exploits the dynamic phase response of the two BPSK signal injected oscillators. As proofs of concept, a 300-MHz receiver/demodulator and an 868/915-MHz industrial- scientific-medical band receiver with digital tuning were implemented in 90-nm bulk CMOS technology. The 300-MHz RX/demod has an active die area of 0.04 mm2, RF input sensitivity of -34 dBm at 1 Mb/s, and consumes just 120 μW from a 1-V supply. The energy efficiency of 0.12 nJ/bit is among the best reported to date for low-power coherent demodulator. Based on the same architecture, the 868/915-MHz BPSK receiver prototype has an active die area of 0.04 mm2, an RF input sensitivity of -50 dBm at 2 Mb/s, and consumes only 216 μW from a 1.2-V supply (0.11 nJ/bit). Digital control of the injection-locked oscillator offset frequencies is implemented on-chip. © 2011 IEEE.

Loading Institute for Microelectronics Stuttgart IMS CHIPS collaborators
Loading Institute for Microelectronics Stuttgart IMS CHIPS collaborators