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Inspur Beijing Electronic Information Industry Co. | Date: 2015-01-12

A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Zhang X.,Xi'an University of Science and Technology | Wang E.,Inspur Beijing Electronic Information Industry Co. | Tang F.,Shanghai JiaoTong University | Yang M.,Xi'an University of Science and Technology | And 2 more authors.
Neurocomputing | Year: 2013

Transient fault is a critical concern in the reliability of microprocessor system. The software fault tolerance is more flexible and lower in cost than the hardware fault tolerance. And also, as architectural trends point toward multicore designs, there is substantial interest in adapting parallel and redundancy hardware resources for transient fault tolerance. The paper proposes a process-level fault tolerance technique, a software-centric approach, which efficiently schedules and synchronizes redundancy processes with ccNUMA processors redundancy. So it can improve efficiency of redundancy processes running and reduce time and space overhead. The paper focuses on the researching of redundancy processes error detection and handling method. A real prototype is implemented that is designed to be transparent to the application. The test results show that the system can timely detect soft errors of CPU and memory that cause the redundancy processes exception, and meanwhile ensure that the services of the application are uninterrupted and delayed shortly. © 2013 Elsevier B.V.

Zhang B.,National University of Defense Technology | Xu S.,Academy of Armored force Engineering | Zhang F.,Inspur Beijing Electronic Information Industry Co. | Bi Y.,Naval Academy of Armament | Huang L.,Central South University
2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce, AIMSEC 2011 - Proceedings | Year: 2011

Lots of toolboxes of accelerating MatLab using GPU are available now[1], but, users are confused by which toolbox is best suitable for a particular task. Three toolboxes-Jacket, GPUmat, and Parallel Computing Toolbox of MatLab are selected. For each toolbox, its advantages and pitfalls are reviewed, with an aim to allow the reader to identify which toolbox is appropriate for a given task. Strategies of whether a function should execute on GPU are given after a formula analysis. The analysis is also a framework for program automatically decides which function is cost-efficient to execute on GPU. A series of benchmark of different types of computing, including data transfer between GPU and CPU, data matrix Generation, matrix operation and GPU functions were tested in all three toolboxes. And the results show that Jacket is the best one. Some advices to improve the performance of toolboxes are given in the end. © 2011 IEEE.

Song Q.,Tianjin University | Mao L.,Tianjin University | Xie S.,Tianjin University | Kang Y.,Inspur Beijing Electronic Information Industry Co.
Journal of Semiconductors | Year: 2015

This paper presents a modified regulated cascode (RGC) transimpedance amplifier (TIA) with a novel pre-equalized technique. The pre-equalized circuit employed the broadband series inductive π-network and Gm-boosting technique. The introduction of this technique compensates the transferred signal at the input port of the TIA without an increase in power dissipation. Furthermore, a novel miller capacitance degeneration method is designed in the gain stage for further bandwidth improvement. The TIA is realized in UMC 0.18 πm CMOS technology and tested with an on-chip 0.3 pF capacitor to emulate a photodetector (PD). The measured transimpedance gain amounts to 57 dBΩ with a -3 dB bandwidth of about 8.2 GHz and consumes only 22 mW power from a single 1.8 V supply. © 2015 Chinese Institute of Electronics.

Zhang D.,HIGH-TECH | Wu N.,HIGH-TECH | Li X.,Inspur Beijing Electronic Information Industry Co.
Proceedings - 4th International Conference on Computational and Information Sciences, ICCIS 2012 | Year: 2012

With the popularization of informatization and the rapid development of modern service industry in the modern society, numerous providers are seeking customers to sell their services. In the meantime, customers' requirements are much different and they are having a much wider range of options. The study describes the servitization of real resources by studying on service resources so that they become service resources. The paper discusses the individualized requirements of customers. A service model is set to help both providers and customers to take part in services. © 2012 IEEE.

Zheng H.,Xi'an University of Science and Technology | Zhang X.,Xi'an University of Science and Technology | Wang E.,Inspur Beijing Electronic Information Industry Co. | Wu N.,Inspur Beijing Electronic Information Industry Co. | Dong X.,Xi'an University of Science and Technology
Proceedings - 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, ICIS 2012 | Year: 2012

Driver faults are the main reasons of causing failure in operating system. In order to address this issue and improve the kernel reliability, this paper presents an intelligent kernelmode driver enhancement mechanism - StyleBox which can limit the driver's rights to access kernel by a private page table and a call control list. This method captures a variety of type errors, synchronization errors and behavior errors of the driver, and intelligently predicts and rapidly recovers driver errors. Experimental results show that StyleBox can effectively detect and deal with driver errors, and obviously improve the reliability of the operating system. © 2012 IEEE.

Wang E.D.,HIGH-TECH | Wu N.,HIGH-TECH | Li X.,Inspur Beijing Electronic Information Industry Co.
Proceedings - 2013 International Conference on Computational and Information Sciences, ICCIS 2013 | Year: 2013

With the development of cloud computing, many critical applications have been supported to provide many key services in the cloud computing. So the availability of cloud computing services turns to be higher and higher. Because resources of cloud computing are distributed, dynamic and heterogeneous, traditional research on availability cannot be good to adapt to the cloud computing new features. This paper does research on QoS-oriented cloud computing resources availability. First, a monitoring model of cloud computing resources availability is created. Then, according to the dynamic process of the cloud computing service, the availability of cloud computing resources is analyzed from QoS of a single cloud resource node which is described by common attribution and special attribution to QoS of some cloud resources which are connected by series model, parallel model and mix model to provide service. According to the three models and the analysis of the single cloud service resource, the availability of cloud computing service is monitored. © 2013 IEEE.

Feng K.,Hubei University | Ma W.,Hubei University | Huang W.,Hubei University | Zhang Q.,Inspur Beijing Electronic Information Industry Co. | Gong Y.,Hubei University
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

Galois Field arithmetic is the basis of LRC, RS and many other erasure coding approaches. Traditional implementations of Galois Field arithmetic use multiplication tables or discrete logarithms, which limit the speed of its computation. The Intel Many Integrated Core (MIC) Architecture provides 60 cores on chip and very wide 512-bit SIMD instructions, attractive for data intensive applications. This paper demonstrates how to leverage SIMD instructions and shared memory multiprocessing on MIC to perform Galois Field arithmetic. The experiments show that the performance of the computation is significantly enhanced. © 2013 IFIP International Federation for Information Processing.

Zhang X.,Xi'an University of Science and Technology | Yang Y.,Xi'an University of Science and Technology | Wang E.,Inspur Beijing Electronic Information Industry Co. | You I.,Korea University | Dong X.,Xi'an University of Science and Technology
International Journal of Ad Hoc and Ubiquitous Computing | Year: 2015

To achieve the software fault tolerance at runtime, based on runtime verification techniques, this paper proposes a runtime model of running program, which is used to define the actions and constrains for runtime software fault management. This model contains the descriptions of event, path, scope and adjustment. A runtime fault management system prototype, which mainly includes the rule description, event acquisition, fault diagnosis and handling, is implemented to verify the model. Two test cases are used to estimate the effect of the prototype, and the results show that this method can handle faults successfully at runtime. Copyright © 2015 Inderscience Enterprises Ltd.

Inspur Beijing Electronic Information Industry CO. | Date: 2012-03-02

A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.

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