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Song Q.,Tianjin University | Mao L.,Tianjin University | Xie S.,Tianjin University | Kang Y.,Inspur Beijing Electronic Information Industry Co.
Journal of Semiconductors | Year: 2015

This paper presents a modified regulated cascode (RGC) transimpedance amplifier (TIA) with a novel pre-equalized technique. The pre-equalized circuit employed the broadband series inductive π-network and Gm-boosting technique. The introduction of this technique compensates the transferred signal at the input port of the TIA without an increase in power dissipation. Furthermore, a novel miller capacitance degeneration method is designed in the gain stage for further bandwidth improvement. The TIA is realized in UMC 0.18 πm CMOS technology and tested with an on-chip 0.3 pF capacitor to emulate a photodetector (PD). The measured transimpedance gain amounts to 57 dBΩ with a -3 dB bandwidth of about 8.2 GHz and consumes only 22 mW power from a single 1.8 V supply. © 2015 Chinese Institute of Electronics. Source

Zhang D.,HIGH-TECH | Wu N.,HIGH-TECH | Li X.,Inspur Beijing Electronic Information Industry Co.
Proceedings - 4th International Conference on Computational and Information Sciences, ICCIS 2012 | Year: 2012

With the popularization of informatization and the rapid development of modern service industry in the modern society, numerous providers are seeking customers to sell their services. In the meantime, customers' requirements are much different and they are having a much wider range of options. The study describes the servitization of real resources by studying on service resources so that they become service resources. The paper discusses the individualized requirements of customers. A service model is set to help both providers and customers to take part in services. © 2012 IEEE. Source

Wang E.D.,HIGH-TECH | Wu N.,HIGH-TECH | Li X.,Inspur Beijing Electronic Information Industry Co.
Proceedings - 2013 International Conference on Computational and Information Sciences, ICCIS 2013 | Year: 2013

With the development of cloud computing, many critical applications have been supported to provide many key services in the cloud computing. So the availability of cloud computing services turns to be higher and higher. Because resources of cloud computing are distributed, dynamic and heterogeneous, traditional research on availability cannot be good to adapt to the cloud computing new features. This paper does research on QoS-oriented cloud computing resources availability. First, a monitoring model of cloud computing resources availability is created. Then, according to the dynamic process of the cloud computing service, the availability of cloud computing resources is analyzed from QoS of a single cloud resource node which is described by common attribution and special attribution to QoS of some cloud resources which are connected by series model, parallel model and mix model to provide service. According to the three models and the analysis of the single cloud service resource, the availability of cloud computing service is monitored. © 2013 IEEE. Source

Feng Z.,Inspur Beijing Electronic Information Industry Co. | Guo H.,Dalian University of Technology | Wang Y.,Dalian University of Technology | Yu Y.,Queensland University of Technology | And 3 more authors.
2014 13th International Conference on Control Automation Robotics and Vision, ICARCV 2014 | Year: 2014

Recently, we have developed a tensor-decomposition based compressed sensing (CS) method for dynamic magnetic resonance imaging (dMRI) [1]. The proposed CS-dMRI method exploits the sparsity of the multi-dimensional MRI signal using Higher-order singular value decomposition (HOSVD). Our preliminary study indicates that, compared with conventional approaches, the proposed CS method offers further acceleration in acquisition and also improves image quality. To further enhance the algorithm efficiency, in this work, we present a parallelized implementation of the HOSVD-based CS reconstructions using a graphics processing unit (GPU). The cine cardiac MRI study indicated the efficiency and accuracy of the GPU-accelerated high-dimensional CS-dMRI method. © 2014 IEEE. Source

Inspur Beijing Electronic Information Industry CO. | Date: 2012-03-02

A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.

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