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Santa Clara, CA, United States

The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for sensing a voltage and/or temperature from an integrated circuit device such as a Serializer/Deserializer (SerDes) integrated circuit device. But it will be recognized that the technique can be used for monitoring other system on chip devices, such as micro-controllers, digital signal processors, microprocessors, networking devices, application specific integrated circuits, and other integrated circuit devices that may desire on-chip temperature and/or voltage sensing capability.


The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. A feedback mechanism is provided for adjusting the transmission power levels. There are other embodiments as well.


Patent
Inphi | Date: 2015-12-18

Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.


A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.


Patent
Inphi | Date: 2015-03-23

The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

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