Santa Clara, CA, United States
Santa Clara, CA, United States

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The present invention relates to integrated circuits. More specifically, embodiments of the present invention provide methods and systems for determining temperatures of an integrated circuit using an one-point calibration technique, where temperature is determined by a single temperature measurement and calculation using known electrical characteristics of the integrated circuit.


In an example, the present invention includes an integrated system on chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device.


A system and method for calibrating an optical module. The optical module including a microprocessor with non-volatile memory is provided at a calibration station for measuring calibrated value of a device parameter against raw values starting from minimum value in each of multiple zones of a primary parameter with one or more secondary parameters at least being set to a basis calibration point to determine coefficients for generating a N-spline function for the multiple zones and multiple multipliers for each zone corresponding to multiple calibration points. The coefficients and multiple multipliers are stored in the non-volatile memory and reused respectively for calculating a basis calibrated value based on any current raw value of the primary parameter a N-spline function in particular zone and for determining a final multiplier by interpolation of the multiple multipliers associated with the one or more secondary parameters, leading to a calibrated value for any condition.


Method and devices of controlling wavelengths in two-channel DEMUX/MUX in silicon photonics are provided. The two-channel DEMUX/MUX includes a waveguide-based delay-line-interferometer at least in receiver portion of a two-channel transceiver for DWDM optical transmission loop and is configured to split a light wave with combined two-wavelengths into one light wave with locked one channel wavelength and another light wave with locked another channel wavelength. The waveguide-based delayed-line interferometer (DLI) is characterized by a free-spectral-range configured to be equal to twice of channel spacing. The method includes tuning heater of DLI in receiver of each two-channel transceiver by using either low-frequency dither signals added on MZMs associated with respective two channels as feedback signal or one DFB laser wavelength tapped from an input of transmitter portion at one channel before or after the MZMs as a direct wavelength reference to feed into an output of receiver portion at another channel.


In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate.


Patent
Inphi | Date: 2017-01-16

In an example, the present invention includes an integrated system on chip device. The device has a variable bias block configured with the control block, the variable bias block being configured to selectively tune each of a plurality of laser devices provided on the silicon photonics device to adjust for at least a wavelength of operation, a fabrication tolerance, and an extinction ratio.


In an example, the present invention includes an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.


Patent
Inphi | Date: 2017-03-06

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.


Patent
Inphi | Date: 2017-02-15

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.


A Pulse Amplitude Modulated (PAM) optical device utilizing multiple wavelengths, features a communications interface having enhanced diagnostics capability. New registers are created to house additional diagnostic information, such as error rates. The diagnostic information may be stored in raw form, or as processed on-chip utilizing local resources.

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