Taoyuan, Taiwan
Taoyuan, Taiwan

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Patent
Inotera Memories | Date: 2015-10-15

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.


Patent
Inotera Memories | Date: 2015-10-27

Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.


Patent
Inotera Memories | Date: 2015-11-16

A semiconductor structure and a method of fabricating thereof are provided. The method includes following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.


Patent
Inotera Memories | Date: 2015-11-27

The present invention provides a method and a fault isolation system for detecting errors in an IC circuit. One feature of the present invention is using the movable second probe to scan and acquire output signal through the vias or metal line structure of diagnostic area along the detecting line, so as to find the fault location precisely, and another feature of the present invention is using the cutter and conjunction with above method to narrow down the fault range. The cutter is used to electrically isolating the portion of diagnostic area step by step for approaching the fault location. By this method can help to save lots of analysis time and also makes the minor fault localization possible.


Patent
Inotera Memories | Date: 2015-07-09

A recoverable device for memory product includes a substrate, a plurality of device dies and at least one local interconnect layer. The device dies are embedded inside the substrate. The at least one local interconnect layer is disposed on an upper surface of the substrate, and configured to route the device dies to a plurality of electrical terminals on an uppermost surface of the local interconnect layer relative to the substrate.


Patent
Inotera Memories | Date: 2015-10-30

A semiconductor device includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress-relief feature is embedded in the molding compound within a peripheral area adjacent to the chip mounting area. A second stress-relief feature is embedded in the molding compound within the chip mounting area. The first stress-relief feature is composed of a first material. The second stress-relief feature is composed of a second material that is different from the first material.


Patent
Inotera Memories | Date: 2015-06-04

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.


Patent
Inotera Memories | Date: 2015-06-03

A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.


Patent
Inotera Memories | Date: 2015-06-05

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is contacted with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.


Patent
Inotera Memories | Date: 2015-06-04

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

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