Inotera Memories

Taoyuan, Taiwan

Inotera Memories

Taoyuan, Taiwan
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Patent
Inotera Memories | Date: 2015-11-16

A semiconductor structure and a method of fabricating thereof are provided. The method includes following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.


Patent
Inotera Memories | Date: 2015-11-27

The present invention provides a method and a fault isolation system for detecting errors in an IC circuit. One feature of the present invention is using the movable second probe to scan and acquire output signal through the vias or metal line structure of diagnostic area along the detecting line, so as to find the fault location precisely, and another feature of the present invention is using the cutter and conjunction with above method to narrow down the fault range. The cutter is used to electrically isolating the portion of diagnostic area step by step for approaching the fault location. By this method can help to save lots of analysis time and also makes the minor fault localization possible.


Patent
Inotera Memories | Date: 2015-07-31

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.


Patent
Inotera Memories | Date: 2015-07-28

An electrostatic chuck includes a chuck base and cooling pipes. The chuck base has at least four cooling zones, in which the cooling zones viewed at a direction normal to the chuck base are fan-shaped. The cooling pipes are respectively disposed in the cooling zones of the chuck base. Therefore, the cooling pipes disposed in the different cooling zones can be controlled individually.


Patent
Inotera Memories | Date: 2015-07-30

A memory device and a method for fabricating thereof are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a contact structure. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The contact structure is over the substrate and electrically connected to one of the first active region and the second active region. The contact structure includes a metal portion directly in contact with one of the first active region and the second active region.


Patent
Inotera Memories | Date: 2015-09-09

A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.


Patent
Inotera Memories | Date: 2015-08-25

A method for fabricating a wafer level package is disclosed. A substrate having a top surface and a bottom surface is provided. A first dielectric layer is formed on the top surface. A redistribution layer (RDL) is formed on the first dielectric layer. The RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer. A first passivation layer is formed on the RDL. Bumps are formed in the first passivation layer. A chip is mounted on the RDL. The chip is electrically connected to the metal layer through the bumps. A molding compound is applied on the first passivation layer and around the chip. The bottom surface of the substrate is grinded until a remaining thickness of the substrate is reached. A plurality of through substrate vias is formed in the substrate.


Patent
Inotera Memories | Date: 2015-10-15

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.


Patent
Inotera Memories | Date: 2015-10-27

Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.


Patent
Inotera Memories | Date: 2015-06-04

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

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