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Taoyuan, Taiwan

Patent
Inotera Memories | Date: 2015-05-04

A non-floating vertical transistor includes a substrate and a protuberant structure extending from the substrate. A segregating pillar is inside the protuberant structure. A pair of segregated bit-lines which are segregated by the segregating pillar is disposed in the substrate and in the protuberant structure and adjacent to the bottom of the segregating pillar. A gate oxide layer is attached to the sidewall of the protuberant structure. A word-line is adjacent to the gate oxide layer so that the gate oxide layer is sandwiched between the word-line and a doped deposition layer.


A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained SiGe layer, an epitaxial Si layer and a second strained SiGe layer. The first strained SiGe layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained SiGe layer. The second strained SiGe layer is located on the epitaxial Si layer. In the surface layer of the second strained SiGe layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.


Patent
Inotera Memories | Date: 2014-04-10

A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.


The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.


Patent
Inotera Memories | Date: 2014-05-30

A semiconductor structure includes a substrate having thereon a conductive region, at least one cylinder-shaped container on the conductive region, and a supporting structure having at least two stripe shaped portions arranged in parallel to each other and at least one retaining ring between the two stripe shaped portions. The retaining ring retains and structurally supports the cylinder-shaped container electrode.

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