Lausanne, Switzerland
Lausanne, Switzerland

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Van Der Plas G.,IMEC | Limaye P.,IMEC | Loi I.,University of Bologna | Mercha A.,IMEC | And 35 more authors.
IEEE Journal of Solid-State Circuits | Year: 2011

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes Vth shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 mm2) and power (3%) overhead. © 2010 IEEE.


Loi I.,University of Bologna | Marchal P.,IMEC | Pullini A.,INoCs | Benini L.,University of Bologna
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

Networks-on-chip have been developed in the last few years to address the scalability challenges of global on-chip communication. VLSI technology is now rapidly moving into vertical stacking to overcome fundamental communication and integration bottlenecks, however this technology is not mature yet, and significant reliability challenges must be overcome. In this paper we describe our effort in establishing a 3DNoC design flow and in designing circuits and architectural solutions for variability and reliability characterization and tolerance. ©2010 IEEE.


Kakoee M.R.,University of Bologna | Sathanur A.,IMEC | Pullini A.,INoCs | Huisken J.,IMEC | Benini L.,University of Bologna
Proceedings of the International Symposium on Low Power Electronics and Design | Year: 2010

Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade-off performance and power in a fine-grained manner. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up-to 45% while achieving more than 50% lower power as compared to single-V dd implementations. Copyright 2010 ACM.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2009.3.2 | Award Amount: 4.12M | Year: 2010

The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict component oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints. Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale IC fabrication technologies raises the need to build reliable systems out of unreliable components.\nThe NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability.\nAbove all, the NaNoC design platform fosters the tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.


De Micheli G.,Ecole Polytechnique Federale de Lausanne | Seiculescu C.,Ecole Polytechnique Federale de Lausanne | Murali S.,Ecole Polytechnique Federale de Lausanne | Benini L.,University of Bologna | And 2 more authors.
Proceedings - Design Automation Conference | Year: 2010

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation. © Copyright 2010 ACM.


Murali S.,iNoCs | Murali S.,Ecole Polytechnique Federale de Lausanne | Benini L.,University of Bologna | De Micheli G.,Ecole Polytechnique Federale de Lausanne
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | Year: 2010

Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The3DICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of. Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs.


Kumar A.S.,Indian Institute of Technology Madras | Kumar M.P.,Indian Institute of Technology Madras | Muraliy S.,INoCs | Kamakoti V.,Indian Institute of Technology Madras | And 2 more authors.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 | Year: 2011

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect. Hence, reducing the buffering overhead of Networks on Chips (NoCs) is an important problem. For application-specific designs, the network utilization across the different links and switches is non-uniform, thereby requiring a buffer sizing approach that tackles the non uniformity. Moreover, congestion effects that occur during network operation needs to be captured when sizing the buffers. To this end, we propose a two-phase algorithm to size the switch buffers in NoCs. Our algorithm considers both the static (based on bandwidth and latency requirements) and dynamic (based on simulation) effects when sizing buffers. Our experiments show that the application of the algorithm results in 42% reduction in amount of buffering required to meet the application constraints when compared to a standard buffering approach. © 2011 IEEE.


Kumar A.S.,Indian Institute of Technology Madras | Kumar M.P.,Indian Institute of Technology Madras | Murali S.,INoCs | Kamakoti V.,Indian Institute of Technology Madras | And 2 more authors.
Journal of Electrical and Computer Engineering | Year: 2012

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach. Copyright © 2012 Anish S. Kumar et al.


Kumar M.P.,Indian Institute of Technology Madras | Kumar A.S.,Indian Institute of Technology Madras | Murali S.,INOCS | Benini L.,University of Bologna | Veezhinathan K.,Indian Institute of Technology Madras
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 | Year: 2011

Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floorplanner. Our experiments on many SoC benchmarks show a reduction of 8-10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches. © 2011 IEEE.


Kumar M.P.,Indian Institute of Technology Madras | Murali S.,INoCs | Veezhinathan K.,Indian Institute of Technology Madras
IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India) | Year: 2012

Interconnects have become the chief bottleneck in today's era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs. Copyright © 2012 by the IETE.

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