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Murali S.,INoCs | Murali S.,Ecole Polytechnique Federale de Lausanne | Benini L.,University of Bologna | De Micheli G.,Ecole Polytechnique Federale de Lausanne
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | Year: 2010

Three-dimensional integrated circuits, where multiple silicon layers are stacked vertically have emerged recently. The3DICs have smaller form factor, shorter and efficient use of wires and allow integration of diverse technologies in the same device. The use of. Networks on Chips (NoCs) to connect components in a 3D chip is a necessity. In this short paper, we present an outline on designing application-specific NoCs for 3D ICs. Source

Loi I.,University of Bologna | Marchal P.,IMEC | Pullini A.,INoCs | Benini L.,University of Bologna
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | Year: 2010

Networks-on-chip have been developed in the last few years to address the scalability challenges of global on-chip communication. VLSI technology is now rapidly moving into vertical stacking to overcome fundamental communication and integration bottlenecks, however this technology is not mature yet, and significant reliability challenges must be overcome. In this paper we describe our effort in establishing a 3DNoC design flow and in designing circuits and architectural solutions for variability and reliability characterization and tolerance. ©2010 IEEE. Source

Kakoee M.R.,University of Bologna | Sathanur A.,IMEC | Pullini A.,INoCs | Huisken J.,IMEC | Benini L.,University of Bologna
Proceedings of the International Symposium on Low Power Electronics and Design | Year: 2010

Near-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade-off performance and power in a fine-grained manner. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up-to 45% while achieving more than 50% lower power as compared to single-V dd implementations. Copyright 2010 ACM. Source

Kumar A.S.,Indian Institute of Technology Madras | Kumar M.P.,Indian Institute of Technology Madras | Muraliy S.,INoCs | Kamakoti V.,Indian Institute of Technology Madras | And 2 more authors.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 | Year: 2011

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect. Hence, reducing the buffering overhead of Networks on Chips (NoCs) is an important problem. For application-specific designs, the network utilization across the different links and switches is non-uniform, thereby requiring a buffer sizing approach that tackles the non uniformity. Moreover, congestion effects that occur during network operation needs to be captured when sizing the buffers. To this end, we propose a two-phase algorithm to size the switch buffers in NoCs. Our algorithm considers both the static (based on bandwidth and latency requirements) and dynamic (based on simulation) effects when sizing buffers. Our experiments show that the application of the algorithm results in 42% reduction in amount of buffering required to meet the application constraints when compared to a standard buffering approach. © 2011 IEEE. Source

Kumar M.P.,Indian Institute of Technology Madras | Kumar A.S.,Indian Institute of Technology Madras | Murali S.,INoCs | Benini L.,University of Bologna | Veezhinathan K.,Indian Institute of Technology Madras
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 | Year: 2011

Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floorplanner. Our experiments on many SoC benchmarks show a reduction of 8-10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches. © 2011 IEEE. Source

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