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Huang C.,Tsinghua University | Wu K.,Tsinghua University | Wang Z.,Tsinghua University | Wang Z.,Innovation Center for Micro Nanoelectronics and Integrated System
IEEE Transactions on Electron Devices

Through-silicon-vias (TSVs) with air-gap insulators have the advantages of low capacitance and low thermal stress. This paper reports the design, fabrication, and characterization of new TSVs with combined air/SiO2 insulators. Sacrificial technologies based on heat decomposition of poly(propylene carbonate) and reactive ion etching of benzocyclobutene have been developed to fabricate uniform and high aspect-ratio air gaps. Air gaps with a thickness of 0.8 μm and an aspect ratio of 62.5:1 have been successfully fabricated. Measurement results show that the SiO2 liner is able to eliminate the impacts of residues of the sacrificial polymers, and the TSVs with air/SiO2 have low capacitances and leakage currents at both room temperature and high temperature, constant minimum capacitance, and good temperature stability. © 2015 IEEE. Source

Yue M.,Tsinghua National Laboratory for Information Sciences and Technology | Wu D.,Tsinghua National Laboratory for Information Sciences and Technology | Wang Z.,Tsinghua National Laboratory for Information Sciences and Technology | Wang Z.,Innovation Center for Micro Nanoelectronics and Integrated System
IEEE Sensors Journal

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an 8 × 8 array has been fabricated using 0.5-μm CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method. © 2001-2012 IEEE. Source

Du Y.,Tsinghua University | Song Z.,Tsinghua University | Zhu H.,Tsinghua University | Wang Z.,Tsinghua University | Wang Z.,Innovation Center for Micro Nanoelectronics and Integrated System
IEEE Transactions on Components, Packaging and Manufacturing Technology

This paper reports a method of fabrication for small-feature-sized nickel (Ni) microbumps on gold (Au) using a newly developed technique called electroless Ni plating with noncontact induction (ENPNI). This technique, differing from conventional electroless Ni plating with contact induction (ENPCI), which directly connects an active metal with an inactive metal to induce Ni electrochemical reaction, is characterized by separation of the active metal and the target metal. The mechanism of ENPNI is interpreted by employing the electric-double layer theory, and some phenomena are explained by the proposed mechanism. Ni microbumps with a diameter of 3-6 μm and a height of 3-4 μm have been successfully fabricated using ENPNI. The resistance of the Ni microbumps is measured, and yield and uniformity are evaluated. By breaking the restriction of contact, ENPNI has the advantages of no need for pretreatment and contact induction, allowing fabrication of microbumps with small feature sizes for applications in which direct contact of an active induction metal is impossible. © 2011-2012 IEEE. Source

Lu G.,Peking University | Wang Y.,Peking University | Wang Y.,Innovation Center for Micro Nanoelectronics and Integrated System | Zhang L.,Peking University | And 4 more authors.
Science China Information Sciences

Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protection devices for integrated circuits. The layout strategy of ggNMOS greatly influences its ESD protection characteristics. Layout strategies forvariation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics. © 2014 Science China Press and Springer-Verlag Berlin Heidelberg Source

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