Andia L.,Innovation and Collaborative Research |
Andia L.,University of Marne-la-Vallee |
Belot D.,Innovation and Collaborative Research |
Villegas M.,University of Marne-la-Vallee |
Baudoin G.,University of Marne-la-Vallee
33rd IEEE Sarnoff Symposium 2010, Conference Proceedings | Year: 2010
A 23 dBm class E power amplifier (PA) has been designed and simulated at 3.7 GHZ using a 130 nm CMOS-SOI technology. The PA is a single stage, single ended cascode formed by a thin oxide transistor as common source device and a laterally diffused MOS (LDMOS) transistor as common gate. Fully integrated high current inductor is used as part of the class E wave shaping network. At 3.7 GHz, the PA achieves more than 60% PAE and a gain of 17 dB with 6 dBm driving signal.