Information and Communications Core Technology Research Laboratory

Daejeon, South Korea

Information and Communications Core Technology Research Laboratory

Daejeon, South Korea

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Park N.-M.,Information and Communications Core Technology Research Laboratory | Cho D.-H.,Information and Communications Core Technology Research Laboratory | Lee K.-S.,ETRI
ETRI Journal | Year: 2015

In this article, a study of a flower like nanostructured CdS buffer layer for improving the performance of a submicron-thick CuIn1-xGaxSe2 (CIGS) solar cell (SC) is presented. Both its synthesis and properties are discussed in detail. The surface reflectance of the device is dramatically decreased. SCs with flower like nanostructured CdS buffer layers enhance short-circuit current density, fill factor, and open-circuit voltage. These enhancements contribute to an increase in power conversion efficiency of about 55% on average compared to SCs that don’t have a flower like nanostructured CdS buffer layer, despite them both having the same CIGS light absorbing layer. © 2015 ETRI.


Heo S.,IT Convergence Technology Research Laboratory | Oh J.,Information and Communications Core Technology Research Laboratory | Kim M.,Information and Communications Core Technology Research Laboratory | Suk J.-H.,Information and Communications Core Technology Research Laboratory | And 3 more authors.
ETRI Journal | Year: 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a 0.18 Îm BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive. © 2015 ETRI.


Kim M.,Information and Communications Core Technology Research Laboratory | Heo S.,IT Convergence Technology Research Laboratory | Oh J.,Information and Communications Core Technology Research Laboratory | Suk J.-H.,Information and Communications Core Technology Research Laboratory | And 3 more authors.
ETRI Journal | Year: 2015

This paper presents an advanced sensorless permanent magnet (PM) brushless motor controller integrated circuit (IC) employing an automatic lead-angle compensator. The proposed IC is composed of not only a sensorless sinewave motor controller but also an isolated gate-driver and current self-sensing circuit. The fabricated IC operates in sensorless mode using a position estimator based on a sliding mode observer and an open-loop start-up. For high efficiency PM brushless motor driving, an automatic leadangle control algorithm is employed, which improves the efficiency of a PM brushless motor system by tracking the minimum copper loss under various load and speed conditions. The fabricated IC is evaluated experimentally using a commercial 200 W PM brushless motor and power switches. The proposed IC is successfully operated without any additional sensors, and the proposed algorithm maintains the minimum current and maximum system efficiency under 0 N•m to 0.8 N•m load conditions. The proposed IC is a feasible sensorless speed controller for various applications with a wide range of load and speed conditions. © 2015 ETRI.


Oh J.,Information and Communications Core Technology Research Laboratory | Kim M.,Information and Communications Core Technology Research Laboratory | Heo S.,IT Convergence Technology Research Laboratory | Suk J.-H.,Information and Communications Core Technology Research Laboratory | And 3 more authors.
ETRI Journal | Year: 2015

This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor currentâ€"sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W. © 2015 ETRI.


Jung S.-W.,Information and Communications Core Technology Research Laboratory | Choi Z.J.-S.,Information and Communications Core Technology Research Laboratory | Koo J.B.,Information and Communications Core Technology Research Laboratory | Park C.W.,Information and Communications Core Technology Research Laboratory | And 4 more authors.
ECS Solid State Letters | Year: 2014

We demonstrate stretchable organic thin-film transistors (OTFTs) on a polyimide stiff-island/elastomer substrate. All processes are performed entirely at elastomer-compatible temperatures. We confirm the basic properties of the poly(vinylidene fluoridetrifluoroethylene) [P(VDF-TrFE)] with a poly(methyl methacrylate) (PMMA) blended film on the elastomer substrate and evaluate the characteristics of the fabricated stretchable OTFTs. A field-effect mobility of 3.4 × 10-3 cm2 V-1 s-1, an Ion/Ioff ratio greater than 103, a subthreshold voltage swing of 12.5 V/decade, and a gate leakage current of 10-10 A were obtained. The endurable maximum strain was approximately 50% for the OTFTs without degrading the field-effect mobility formed on the elastomers. © 2014 The Electrochemical Society.


Chang W.,Information and Communications Core Technology Research Laboratory | Park Y.-R.,Information and Communications Core Technology Research Laboratory | Mun J.K.,Information and Communications Core Technology Research Laboratory | Ko S.C.,Information and Communications Core Technology Research Laboratory
ETRI Journal | Year: 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide- semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fieldeffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively. © 2016 ETRI.


Suk J.-H.,Information and Communications Core Technology Research Laboratory | Lyuh C.-G.,Information and Communications Core Technology Research Laboratory | Yoon S.,atform Research Center | Roh T.M.,Information and Communications Core Technology Research Laboratory
ETRI Journal | Year: 2015

In this paper, we propose an efficient architecture for a real-time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle-detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual-core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single-core engine operation. In addition, a dual-core structure is used to detect a failure in state machines using rock-step logic to satisfy the ISO26262 standard. The dual-core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry’s 65 nm CMOS process. The single-core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display. © 2015 ETRI.

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