Time filter

Source Type

Da Rocha J.F.,Polytechnic Institute of Lisbon | Dos Santos M.B.,Institute Engineering Of Sistemas E Of Computadores Inesc Id | Dos Santos M.B.,University of Lisbon | Costa J.M.D.,Institute Engineering Of Sistemas E Of Computadores Inesc Id
Journal of Low Power Electronics | Year: 2011

A smart dual slope gate driver for CMOS integrated low voltage DC-DC buck converters is proposed. The proposed driver reduces the switching losses and limits the magnitude of the internal voltage spikes caused by current variations on the parasitic inductances inbuilt in the converter power supply path. The dual slope gate driver has two strengths: a weak (slow) and a strong one (fast) which time duration is dynamically adjusted in order to control the time of the opening phase of the buck convertor active switch when the fastest variation of the current occurs. The magnitude of the voltage spikes in the internal power supply nodes depends on the time derivative of the current in the parasitic inductances, and can be hazardous to the chip, especially when a high current is switched at a high frequency. To overcome this problem, a common solution is to increase the turn-off time of the active switch at a cost of a reduced switching frequency and efficiency. To increase the power density of integrated low voltage DC-DC converters, the switching frequency must be increased and soft switching techniques were proposed to reduce the switching losses and to absorb the parasitic inductances and capacitances. However, these solutions increase the control complexity and cause higher voltage or current stress on the switches. Hard switching converters integrated with low voltage standard CMOS technologies can be used with high switching frequencies if new gate drivers are designed. The proposed smart dual slope gate drive reduces the internal supply voltage spikes of a DC-DC buck converter by dynamically adjusting the driver strength in order to increase the efficiency even with high switching frequencies. The dual slope drive is explained and results from a buck converter designed in a 0.13m standard CMOS technology are discussed in terms of the impact on high level design parameters, mainly on the switching losses and on the voltage spike magnitude reduction. © 2011 American Scientific Publishers All rights reserved. Source

Sadio V.,Institute Engineering Of Sistemas E Of Computadores Inesc Id | Sadio V.,University of Lisbon | Rein F.,Munich University of Applied Sciences | Munker C.,Munich University of Applied Sciences | And 2 more authors.
Journal of Low Power Electronics | Year: 2012

This paper presents an accurate new model for the losses related with charge/discharge process in switched capacitor (SC) DC-DC converters, named from now on inherent losses, considering especially the full integration of the converter. The model was developed for a voltage doubler and it is based on the differential equations of the circuit. It is considered that the output capacitor (COUT ) has dimensions comparable to the flying capacitors (CFLY ). That leads to a more complex, but also more realistic, model of the circuit, especially for fully integrated converters. Usually, in SC DC-DC converters with external capacitors, COUT -CFLY , and a simple RC first order model can be used, but for fully integrated SC DC-DC converters, other techniques are applied to lower the voltage ripple instead of just using a large COUT . Simulations of a voltage doubler were performed to be used as reference and to validate the model that is also compared with other models from recent publications. The results showed that this model is more accurate in calculating the power losses of the voltage doubler across a wide range of CFLY and COUT values, being a model with small complexity. Compared to simulation results, the proposed model presents a maximum relative error around 0.13%, while previous models present maximum errors that are, at least, 6%. This modeling is particularly important because it may be used in the optimization of the SC DC-DC converter taking into account the specifications and area limit, if the dynamic losses associated to the parasitic capacitances in the circuit are considered. Copyright © 2012 American Scientific Publishers. All rights reserved. Source

Jacinto B.,Institute Engineering Of Sistemas E Of Computadores Inesc Id | Jacinto B.,University of Lisbon | Moreira C.,Institute Engineering Of Sistemas E Of Computadores Inesc Id | Moreira C.,University of Lisbon | And 2 more authors.
Journal of Low Power Electronics | Year: 2011

This work proposes a digital implementation of the Sliding Mode Control law in a DC-DC Buck converter. The control law is implemented monitoring only the DC-DC output voltage, and is capable of producing a maximum overshoot/undershoot of 50 mV for load transients from 0 A to 1.5 A and vice versa. The maximum settling time for these conditions at 1.5% is 5.51 μs for a load transient from 1.5 A to 0.15 A. For line transients the DC-DC converter produces minimal overshoot/undershoot. Results are present for the Matlab ® model with the continuous control law and for the final implementation using HSim ® with the digital control law implementation. The ADC is implemented using a current controlled delay line and it is insensitive to layout parasitics, temperature, supply voltage and process parameters changes. The ADC self calibration capability is considered a major original contribution of this work. The ADC and the digital control where designed using AMS CMOS technology C35B4 (0.35 μm). Copyright © 2011 American Scientific Publishers All rights reserved. Source

Discover hidden collaborations