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Romano P.,INESC ID | Quaglia F.,University of Rome La Sapienza
IEEE Transactions on Dependable and Secure Computing

In this paper, we address reliability issues in three-tier systems with stateless application servers. For these systems, a framework called e-Transaction has been recently proposed, which specifies a set of desirable end-to-end reliability guarantees. In this article, we propose an innovative distributed protocol providing e-Transaction guarantees in the general case of multiple, autonomous back-end databases (typical of scenarios with multiple parties involved within a same business process). Differently from existing proposals coping with the e-Transaction framework, our protocol does not rely on any assumption on the accuracy of failure detection. Hence, it reveals suited for a wider class of distributed systems. To achieve such a target, our protocol exploits an innovative scheme for distributed transaction management (based on ad hoc demarcation and concurrency control mechanisms), which we introduce in this paper. Beyond providing the proof of protocol correctness, we also discuss hints on the protocol integration with conventional systems (e.g., database systems) and show the minimal overhead imposed by the protocol. © 2006 IEEE. Source

Palmieri R.,University of Rome La Sapienza | Quaglia F.,University of Rome La Sapienza | Romano P.,INESC ID
Proceedings of the IEEE Symposium on Reliable Distributed Systems

In this work we present OSARE, an active replication protocol for transactional systems that combines the usage of Optimistic Atomic Broadcast with a speculative concurrency control mechanism in order to overlap transaction processing and replica synchronization. OSARE biases the speculative serialization of transactions towards an order aligned with the optimistic message delivery order. However, due to the lock-free nature of its concurrency control algorithm, at high concurrency levels, namely when the probability of mismatches between optimistic and final deliveries is higher, OSARE explores additional alternative transaction serialization orders in a lightweight and opportunistic fashion. A simulation study we carried out in the context of Software Transactional Memory systems shows that OSARE achieves robust performance also in scenarios characterized by non-minimal likelihood of reorder between optimistic and final deliveries, providing remarkable speed-up with respect to state of the art speculative replication protocols. © 2011 IEEE. Source

Janota M.,INESC ID | Marques-Silva J.,University College Dublin
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Quantified Boolean Formulas (QBFs) enable standard representation of PSPACE problems. In particular, formulas with two quantifier levels (2QBFs) enable representing problems in the second level of the polynomial hierarchy (Π2 P, ∑2 P). This paper proposes an algorithm for solving 2QBF satisfiability by counterexample guided abstraction refinement (CEGAR). This represents an alternative approach to 2QBF satisfiability and, by extension, to solving decision problems in the second level of polynomial hierarchy. In addition, the paper presents a comparison of a prototype implementing the presented algorithm to state of the art QBF solvers, showing that a larger set of instances is solved. © 2011 Springer-Verlag. Source

Fernandes B.,INESC ID | Sarmento H.,University of Lisbon
Analog Integrated Circuits and Signal Processing

In this paper we discuss the FPGA design of a 128-point Pipelined FFT processor for a multi-band (MB)-OFDM receiver. We implemented two parallel architectures based on the Xilinx Core Generator. The architectures use two or four smaller FFTs in parallel. Results show that time requirements are fulfill when combining Pipelined, Streaming input/output (I/O) architectures with Radix-2 and Radix-4 operations. For Virtex-4, we need four levels of parallelization, but for Virtex-5 only two. Both circuits were synthesized, placed and routed. We tested the circuits on the FPGA, defining test vectors and analyzing outputs signals with Chipscope. © Springer Science+Business Media, LLC 2011. Source

Vestias M.P.,INESC ID | Neto H.C.,INESC ID
Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011

The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the importance of decimal arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations. A few hardware approaches have been proposed for decimal arithmetic, including addition, subtraction, multiplication and division. Parallel implementations for these operations are very expensive in terms of occupied resources and therefore implementations based on iterative algorithms are good alternatives. In this paper, we propose an iterative decimal multiplier for FPGA that uses binary arithmetic. The circuits were implemented in a Xilinx Virtex 4 FPGA. The results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers. © 2011 IEEE. Source

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