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South Bend, IN, United States

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Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-17

In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities are formed in the substrate, a conductive pad is formed in each cavity, and one or more conductive traces are formed on the substrate. Each conductive trace connects a conductive pad to a location, node, or terminal of the electrical circuit. A part of the substrate is removed to form the assembly that includes the electrical circuit, the one or more conductive traces, and a portion of each conductive pad projecting or protruding from the substrate. The electrical circuit can be formed on the substrate, which can be a PCB, or can be formed on a microchip supported by the substrate, which can be formed of semiconductor material, e.g., a semiconductor wafer.


Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-25

A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.


Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-17

Disclosed is a quilt packaging system that includes a number of microchip substrates, each having one or more quilt package (QP) nodules located on one or more edge surfaces. The microchip substrates are hingedly connected via the QP nodules in an interdigitated manner to form planar or a non-planar structure.


Fay P.,University of Notre Dame | Kopp D.,University of Notre Dame | Lu T.,Indiana Integrated Circuits, LLC | Neal D.,Indiana Integrated Circuits, LLC | And 2 more authors.
IEEE Microwave and Wireless Components Letters | Year: 2014

Ultrawide bandwidth coplanar waveguide interconnects between GaAs chips based on a novel fabrication process are demonstrated. Fabricated structures on 100μm thick GaAs chips exhibited chip-to-chip insertion losses below 1 dB up to 110 GHz, and below 2.2 dB up to 220 GHz from on-wafer S-parameter measurements. A return loss larger than 10 dB from 100 MHz to 220 GHz was measured. The measured responses are consistent with numerical simulations, including the effects of excess solder at the chip-to-chip interface. Numerical simulations indicate that further improvements in performance, with insertion losses as low as 1.1 dB at 220 GHz, should be possible by minimizing the excess solder. © 2001-2012 IEEE.


Fay P.,University of Notre Dame | Bernstein G.H.,University of Notre Dame | Lu T.,Indiana Integrated Circuits, LLC | Kulick J.M.,Indiana Integrated Circuits, LLC
Journal of Infrared, Millimeter, and Terahertz Waves | Year: 2016

Heterogeneous chip-to-chip interconnects with low loss and ultra-wide bandwidths have been demonstrated. Coplanar waveguide-based interconnects between GaAs and Si die have been fabricated and characterized and the results compared to expectations from full-wave electromagnetic simulation. Broadband transmission characteristics were obtained, with insertion losses below 0.3 dB at 100 GHz and below 0.8 dB at frequencies up to 220 GHz demonstrated experimentally. The measured return loss exceeded 11.5 dB at all frequencies up to 220 GHz. The interconnects offer low latency, with a measured group delay of 0.69 ps. The measured results are in good agreement with full-wave simulations, indicating that the measured results do not suffer from significant impairments compared to theoretical predictions. The demonstrated interconnects offer an alternative to conventional approaches to millimeter-wave circuit and system integration, by enabling the compact realization of circuits in the microwave, millimeter-wave, sub-millimeter-wave, and THz frequency regimes in heterogeneous device technologies with very low chip-to-chip insertion loss. © 2016 The Author(s)


Patent
Indiana Integrated Circuits, LLC | Date: 2014-03-14

Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 124.87K | Year: 2014

Indiana Integrated Circuits, LLC (IIC) proposes to develop the customizable, high-performance microchip interconnect technology called Quilt Packaging (QP) to address NASA's requirement for high performance integration of heterogeneous microwave systems. QP is an affordable, scalable, patented edge-interconnect technology for joining microchips of disparate materials and/or process technologies into monolithic-like systems that perform electrically as if they were one chip. QP enables sub-micron chip-to-chip alignment, extremely small (< 10 micron) chip-to-chip gaps, and can be implemented in multiple substrate materials, including SiGe, GaAs, Si, InP, GaSb, SiC, GaN, and more. Quilt Packaging can enable extremely low-loss, wide-bandwidth integration of MMIC modules comprising disparate material systems and/or process technologies. QP has demonstrated less than 0.1 dB insertion loss up to 100 GHz, and under 1 dB out to 220 GHz. Initial reliability testing of QP chipsets have demonstrated no degradation or mechanical issues, having undergone thermal cycling from -40 C to 125 C for over 350 cycles and counting. In addition to excellent microwave performance, QP has the potential for decreasing system size, weight and power. The proposed effort will leverage previous work in GaAs and Si QP to demonstrate a heterogeneously integrated "quilted" chipset of SiGe, GaAs and/or InP chips. Resulting data from this Phase I will directly apply to the design, fabrication and demonstration of a functioning MMIC module in Phase II. Throughout Phase I consideration will be given to NASA system needs and transition to production-level Quilt Package chip fabrication with commercialization partners Research Triangle Institute and Northrop Grumman Corp. for manufacturing scale-up of Quilt Packaging enabled MMIC modules.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.76K | Year: 2013

ABSTRACT: Improvements such as increased array size and better non-uniformity correction have been made to resistive emitter arrays fabricated on silicon (Si). There exist additonal wavelengths of interest whose emitter devices require fabrication in other materials, such as gallium arsenide (GaAs). For both Si and GaAs substrate materials, attempts to"tile"small arrays into larger ones for reasons of cost and design flexibility have met with limited success. Issues such as chip-to-chip I/O pitch, relatively large"seams"created by gaps between adjacent chips, and precision chip alignment all have posed significant problems to tiling smaller chips into larger arrays. Integrating drive and control electronics further complicates this problem. The new electronic packaging technology developed by Indiana Integrated Circuits, LLC and known as"Quilt Packaging"(QP) can alleviate many of the problems associated with tiling arrays, while delivering desired electronic performance, thermal management and design flexibility. QP enables sub-micron chip-to-chip alignment, customizable chip I/O potentially as dense as 10 micron pitch, and can reduce"seams"between array elements to less than 10 microns. The IIC team proposes to integrate QP technology for application to scalable, flexible, lower-cost GaAs-based emitter arrays for a new generation of high-performance infrared scene projector systems. BENEFIT: There is considerable interest from the scene simulation community in the production of large scale IRSP systems for testing large format imagers. Near term commercialization would be the production of IRSP systems based on the gallium arsenide (GaAs) Quilt Packaging processes proposed for this SBIR effort, or their modification to address similar IRSP technologies. If arrays can be tiled on all 4 sides, then emitter arrays will no longer be limited by RIIC size/yield, drastically reducing array cost. Effectively any size array could be fabricated by joining the requisite number of tiles, though power, thermal and carrier size limitations will limit the practical size of a tiled array. Another potential application would apply to large arrays for infrared imaging, and the proposed technology could also be applied to other types of focal plane arrays. In addition to the military/defense market for IR detection arrays, there are significant commercial applications if the cost curve can be bent down enough. Bio-medical, security scanning, standoff detection and manufacturing quality control are all potential markets for low-cost, large-format imaging arrays. It is anticipated that in addition to these known markets, new markets will emerge for IR imagers as the system costs decrease.


Trademark
Indiana Integrated Circuits, LLC | Date: 2012-09-25

Amplifier for wireless communications; Antennas for wireless communications apparatus; Broadband wireless equipment, namely, telecommunications base station equipment for cellular and fixed networking and communications applications; Chip carriers, namely, semiconductor chip housings; Circuit testers; Computer chips; Computer hardware for wireless content delivery; Computer hardware, namely, wireless access point (WAP) devices; Computer hardware, namely, wireless network extenders; Computer hardware, namely, wireless network repeaters; Connectors for electronic circuits; Design libraries, namely, downloadable electronic data files for use in integrated circuit and semiconductor design; Devices for wireless radio transmission; Electric and electronic circuits; Electrical circuit boards; Electronic chips for the manufacturer of integrated circuits; Electronic circuits; Electronic integrated circuits; Integrated circuit handlers, namely, machines for testing integrated circuits; Integrated circuit module; Integrated circuit modules; Integrated circuits; Integrated circuits and integrated circuit cores for use in wireless communications and wireless communication equipment and apparati and digital signal processors (DSP); Large scale integrated circuits; Printed circuit boards; Printed circuit boards (PCBs); Probes for testing integrated circuits; Radar; Radar receivers with amplifiers; Satellite and microwave communications apparatus to transmit communications from a vehicle to another vehicle, or from a vehicle to a satellite; Semiconductor chips; Semiconductor devices; Semiconductor power elements; Semiconductors; Silicon chips; Supercomputers; Very large scale integration (VLSI) semiconductor integrated circuits; Wireless broadband radios.


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