South Bend, IN, United States

Indiana Integrated Circuits, LLC

www.indianaic.com
South Bend, IN, United States

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Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-17

In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities are formed in the substrate, a conductive pad is formed in each cavity, and one or more conductive traces are formed on the substrate. Each conductive trace connects a conductive pad to a location, node, or terminal of the electrical circuit. A part of the substrate is removed to form the assembly that includes the electrical circuit, the one or more conductive traces, and a portion of each conductive pad projecting or protruding from the substrate. The electrical circuit can be formed on the substrate, which can be a PCB, or can be formed on a microchip supported by the substrate, which can be formed of semiconductor material, e.g., a semiconductor wafer.


Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-25

A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.


Patent
Indiana Integrated Circuits, LLC | Date: 2016-10-17

Disclosed is a quilt packaging system that includes a number of microchip substrates, each having one or more quilt package (QP) nodules located on one or more edge surfaces. The microchip substrates are hingedly connected via the QP nodules in an interdigitated manner to form planar or a non-planar structure.


Patent
Indiana Integrated Circuits, LLC and University of Notre Dame | Date: 2017-03-02

First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.


Patent
Indiana Integrated Circuits, LLC | Date: 2015-07-17

Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.


Patent
University of Notre Dame and Indiana Integrated Circuits, LLC | Date: 2017-04-21

First, second, and third integrated devices each include one or more interconnecting structure. Each interconnecting structure includes (i) one or more interconnecting nodules extending from an edge surface of the device, (ii) one or more interconnect voids formed in an edge surface of the device, or (iii) both (i) and (ii). The one or more interconnecting structures on each of the first and second device is mated with the one or more interconnecting structures on the second device. The first integrated device includes a signal output, the third integrated device includes a signal input; and the second integrated device includes a conductor for conducting a signal from the signal output to the signal input.


Patent
Indiana Integrated Circuits, LLC | Date: 2014-03-14

Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 124.87K | Year: 2014

Indiana Integrated Circuits, LLC (IIC) proposes to develop the customizable, high-performance microchip interconnect technology called Quilt Packaging (QP) to address NASA's requirement for high performance integration of heterogeneous microwave systems. QP is an affordable, scalable, patented edge-interconnect technology for joining microchips of disparate materials and/or process technologies into monolithic-like systems that perform electrically as if they were one chip. QP enables sub-micron chip-to-chip alignment, extremely small (< 10 micron) chip-to-chip gaps, and can be implemented in multiple substrate materials, including SiGe, GaAs, Si, InP, GaSb, SiC, GaN, and more. Quilt Packaging can enable extremely low-loss, wide-bandwidth integration of MMIC modules comprising disparate material systems and/or process technologies. QP has demonstrated less than 0.1 dB insertion loss up to 100 GHz, and under 1 dB out to 220 GHz. Initial reliability testing of QP chipsets have demonstrated no degradation or mechanical issues, having undergone thermal cycling from -40 C to 125 C for over 350 cycles and counting. In addition to excellent microwave performance, QP has the potential for decreasing system size, weight and power. The proposed effort will leverage previous work in GaAs and Si QP to demonstrate a heterogeneously integrated "quilted" chipset of SiGe, GaAs and/or InP chips. Resulting data from this Phase I will directly apply to the design, fabrication and demonstration of a functioning MMIC module in Phase II. Throughout Phase I consideration will be given to NASA system needs and transition to production-level Quilt Package chip fabrication with commercialization partners Research Triangle Institute and Northrop Grumman Corp. for manufacturing scale-up of Quilt Packaging enabled MMIC modules.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.76K | Year: 2013

ABSTRACT: Improvements such as increased array size and better non-uniformity correction have been made to resistive emitter arrays fabricated on silicon (Si). There exist additonal wavelengths of interest whose emitter devices require fabrication in other materials, such as gallium arsenide (GaAs). For both Si and GaAs substrate materials, attempts to"tile"small arrays into larger ones for reasons of cost and design flexibility have met with limited success. Issues such as chip-to-chip I/O pitch, relatively large"seams"created by gaps between adjacent chips, and precision chip alignment all have posed significant problems to tiling smaller chips into larger arrays. Integrating drive and control electronics further complicates this problem. The new electronic packaging technology developed by Indiana Integrated Circuits, LLC and known as"Quilt Packaging"(QP) can alleviate many of the problems associated with tiling arrays, while delivering desired electronic performance, thermal management and design flexibility. QP enables sub-micron chip-to-chip alignment, customizable chip I/O potentially as dense as 10 micron pitch, and can reduce"seams"between array elements to less than 10 microns. The IIC team proposes to integrate QP technology for application to scalable, flexible, lower-cost GaAs-based emitter arrays for a new generation of high-performance infrared scene projector systems. BENEFIT: There is considerable interest from the scene simulation community in the production of large scale IRSP systems for testing large format imagers. Near term commercialization would be the production of IRSP systems based on the gallium arsenide (GaAs) Quilt Packaging processes proposed for this SBIR effort, or their modification to address similar IRSP technologies. If arrays can be tiled on all 4 sides, then emitter arrays will no longer be limited by RIIC size/yield, drastically reducing array cost. Effectively any size array could be fabricated by joining the requisite number of tiles, though power, thermal and carrier size limitations will limit the practical size of a tiled array. Another potential application would apply to large arrays for infrared imaging, and the proposed technology could also be applied to other types of focal plane arrays. In addition to the military/defense market for IR detection arrays, there are significant commercial applications if the cost curve can be bent down enough. Bio-medical, security scanning, standoff detection and manufacturing quality control are all potential markets for low-cost, large-format imaging arrays. It is anticipated that in addition to these known markets, new markets will emerge for IR imagers as the system costs decrease.


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