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Sevilla, Spain

Acasandrei L.,IMSE CNM CSIC | Barriga A.,University of Seville
Proceedings of the 2012 International Conference on Image Processing, Computer Vision, and Pattern Recognition, IPCV 2012 | Year: 2012

This paper presents an FPGA face detection embedded system. In order achieve acceleration in the face detection process a hardware-software codesign technique is proposed. The paper describes the face detection acceleration mechanism. It also describes the implementation of an IP module that allows hardware acceleration. Source


Zamarreno-Ramos C.,IMSE CNM CSIC | Kulkarni R.,Texas A&M University | Silva-Martinez J.,Texas A&M University | Serrano-Gotarredona T.,IMSE CNM CSIC | Linares-Barranco B.,IMSE CNM CSIC
IEEE Transactions on Biomedical Circuits and Systems | Year: 2013

This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μ m CMOS. At 500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μ A ( 343 \,μ A for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions. © 2007-2012 IEEE. Source


Zamarreno-Ramos C.,IMSE CNM CSIC | Serrano-Gotarredona T.,IMSE CNM CSIC | Linares-Barranco B.,IMSE CNM CSIC
IEEE Transactions on Biomedical Circuits and Systems | Year: 2012

This paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching mechanism. Using this technique, the link power consumption can be scaled down with the event rate without compromising the maximum system throughput. The proposed technique has been implemented on a typical push/pull low voltage differential signaling (LVDS) circuit, but it can easily be extended to other widely used current mode standards, such as current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL). A proof of concept prototype has been fabricated in 0.35μm CMOS incorporating the proposed driver/receiver pair along with a previously reported switchable serializer/deserializer scheme. At a 500 Mbps bit rate, the maximum event rate is 11 Mevent/s for 32-bit events. In this situation, current consumption is 7.5 mA and 9.6 mA for the driver and receiver, respectively, while differential voltage amplitude is pm 300 mV. However, if event rate is lower than 20-30 Kevent/s, current consumption has a floor of 270μ A for the driver and 570μA for the receiver. The measured ON/OFF switching times are in the order of 1 ns. The serial link could be operated at up to 710 Mbps bit rate, resulting in a maximum 32-bit event rate of 15 Mevent/s. This is the same peak event rate as that obtained with the same SerDes circuits and a non-switched driver/receiver pair. © 2012 IEEE. Source

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