Leuven, Belgium
Leuven, Belgium

Imec, formerly the Interuniversity Microelectronics Centre, is a micro- and nanoelectronics research center headquartered in Leuven, Belgium, with offices in Belgium, the Netherlands, Taiwan, USA, China, India and Japan. Its staff of about 2,000 people includes more than 600 industrial residents and guest researchers. Wikipedia.


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The present disclosure describes methods and devices relating to electrode holding arrangements for bioelectric use. An example electrode holding arrangement includes a piece of flexible material configured to be fixed to a body part and at least one electrode spring element. The at least one electrode spring element is created by cutting out a certain geometric profile from the piece of flexible material. When the piece of flexible material is fixed to the body part having a body tissue surface, and an electrode is attached to the at least one electrode spring element and is positioned on the body tissue surface so that the body tissue surface generates a first force that makes the electrode spring element protrude outside a horizontal plane of the piece of flexible material, the at least one electrode spring element generates a second force that presses the electrode against the body tissue surface.


Patent
Ghent University and Imec | Date: 2016-11-22

A sensor for sensing a substance such as for example glucose. The sensor is implantable in the body of a living creature. The sensor has a photonic integrated circuit, e.g. silicon-photonics integrated circuit, for spectrally processing radiation interacting with the sample. A continuous monitoring system can also include such a sensor.


The present disclosure is directed to an impedance spectroscopy system for bio-impedance measurement. The impedance spectroscopy system includes a signal generator configured to generate a signal with a broadband frequency spectrum and to generate an analog injection current from the signal with the broadband frequency spectrum. The analog injection current has a high pass frequency characteristic. The impedance spectroscopy system also includes an amplifier configured to measure a voltage signal in response to the analog injection current and to simultaneously measure a biopotential signal. Further, the impedance spectroscopy system includes a processor configured to analyze the voltage signal to derive a bio-impedance spectrum as well to derive further information from the biopotential signal.


Patent
Imec and Catholic University of Leuven | Date: 2016-05-09

The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.


Patent
Imec | Date: 2016-08-29

The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.


The present disclosure relates to directed self-assembly using trench assisted chemoepitaxy. An example embodiment includes a method of forming a pre-patterned structure for directing a self-assembly of a self-assembling material that includes a first and a second component having different chemical natures. The method includes providing an assembly includes a substrate, a layer of pinning material overlying the substrate, and a resist pattern overlaying the layer of pinning material. The method also includes modifying a chemical nature of an exposed part of a top surface of the layer of pinning material. The method further includes removing the resist pattern. In addition, the method includes attaching a neutral layer to the layer of pinning material.


Patent
Imec | Date: 2016-09-02

A method for preparing a monocrystalline silicon substrate surface for a subsequent texturing step, the method comprising: removing contaminants from the surface by contacting the surface with a cleaning solution; etching the pre-cleaned surface with an aqueous solution comprising from 12 to 19% by weight, of KOH and/or NaOH; rinsing the etched surface with an aqueous medium at pH from 7 to 10; and contacting the rinsed etched surface with ozonated deionized water at pH from 2 to 4.5, thereby converting the rinsed etched surface into a prepared surface. A method for texturing the prepared surface is also provided.


The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an In_(a)Ga_(b)As structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is Ga_(g)X_(x)P_(p)Sb_(s)Z_(z), where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.


The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P


A method for producing a pillar structure (40) in a semiconductor layer, the method comprising providing a structure comprising, on a main surface, a semiconductor layer (30). A patterned hard mask layer stack (10, 20) is provided on the semiconductor layer that comprises a first layer (20) in contact with the semiconductor layer and a second layer (10) overlying and in contact with the first layer.The semiconductor layer is dry plasma etched using the patterned hard mask layer stack as a mask (Fig. 5(d-g)). The dry plasma etching comprises subjecting the structure to a first plasma (Fig. 5(d)) thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure (41), thereafter subjecting the structure to a second plasma (Fig. 5(f)) thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure (42). A height of the removed first part (41) is greater than a height of the removed second part (42).

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