Leuven, Belgium
Leuven, Belgium

Imec, formerly the Interuniversity Microelectronics Centre, is a micro- and nanoelectronics research center headquartered in Leuven, Belgium, with offices in Belgium, the Netherlands, Taiwan, USA, China, India and Japan. Its staff of about 2,000 people includes more than 600 industrial residents and guest researchers. Wikipedia.

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A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.


Patent
Ghent University and Imec | Date: 2017-05-17

A photonic integrated circuit (10) comprises an input interface (12) adapted for receiving an optical input signal and splitting it into two distinct polarization modes and furthermore adapted for rotating the polarization of one of the modes for providing the splitted signals in a common polarization mode,. The PIC also comprises a combiner (16) adapted for combining the first mode signal and the second mode signal into a combined signal and a decohering means (15) adapted for transforming at least one of the first mode signal and the second mode signal such that the first mode signal and the second mode signal are received by the combiner in a mutually incoherent state. A processing component (17) for receiving and processing said combined signal is also comprised.


Patent
Imec | Date: 2017-01-04

The present invention relates to a conversion circuit (10) comprising- a first input terminal for receiving a digital signal (RFin),- a second input terminal for receiving a bias voltage signal (Vb),- an output terminal for outputting a current,- a first (SW1) and a second (SW2) switch transistor connected to said first input terminal for receiving said digital signal (RFin),- a first (M1) and a second (M2) current source transistor connected to said second input terminal for receiving said bias voltage signal (Vb),whereby said conversion circuit comprises a first branch wherein said first switch transistor is connected to said output terminal via said first current source transistor and a second branch wherein said second current source transistor is connected to said output terminal via said second switch transistor.


Patent
Imec | Date: 2017-03-08

A semiconductor circuit (10) is disclosed, comprising a Front End of Line comprising a plurality of transistors, each of which having a source region (110), a drain region (120) and a gate region (100) arranged between the source region and the drain region and comprising a gate electrode (101). The semiconductor circuit also comprises a buried interconnect (130) that is arranged in the FEOL (160) and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.


The present invention relates to a memory hierarchy being directly connectable to a processor, said memory hierarchy having at least a Level 1, hereinafter termed L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB), said buffer structure comprising a plurality of interconnected wide registers with an asymmetric organization, wider towards said non-volatile memory unit than towards a data path connectable to said processor, said buffer structure and said non-volatile memory unit arranged for being directly connectable to said processor so that data words are selectable to be read or written by said processor.


A memory arrangement comprising a plurality of memory cells arranged in an array structure is described. Each bit line has a bit line capacitance, for storing a charge representative of the state of a selected memory element, whereby the charge is discharged when current flows between pre-charged bit line and a ground line through the selected memory element. At least two memory cells, positioned at different bit lines but on a same word line, are being defined as reference cells, one reference cell being set in a high resistance state and a second reference cell being in a low resistance state. At least those bit lines wherein the reference cells are defined furthermore are interconnected by an equalizing switch, for equalizing the charges on the bit line capacitors of said at least two bit lines.


Patent
Imec, Catholic University of Leuven and Panasonic | Date: 2017-09-27

A method for fabricating a thin-film solid-state battery cell (100) on a substrate (10) comprising a first current collector layer (12) is disclosed, the method comprising: depositing above the first current collector layer (12) a first electrode layer (30), wherein the first electrode layer (30) is a nanoporous composite layer comprising a plurality of pores having pore walls, and wherein the first electrode layer (30) comprises a mixture of a dielectric material and active electrode material particles; depositing above the first electrode layer (30) a porous dielectric layer (40); and depositing directly on the porous dielectric layer (40) a second electrode layer (50), wherein depositing the second electrode layer (50) comprises depositing a porous Ni(OH)_(2) layer by means of a electrochemical deposition process. A thin-film solid-state battery cell (100) and a battery are further disclosed.


Patent
Imec and Catholic University of Leuven | Date: 2017-09-27

The present invention relates to an integrated waveguide structure (280) comprising a substrate (2), a waveguide (281) in or on the substrate (2) and an optical nanoantenna structure (3) for directionally scattering light in the visible and/or the near infrared spectral range. The optical nanoantenna structure (3) is positioned on or above the waveguide (281) such that the directionally scattered light is projected into the waveguide in two opposite directions (283) of the waveguide. The optical nanoantenna structure (3) is composed of a dielectric material having a refractive index that is higher than the refractive index of the waveguide and higher than the refractive index of the surrounding medium. The optical nanoantenna structure (3) is a simply-connected structure having two distinct end portions, and is asymmetric with respect to at least one mirror reflection in a plane that is orthogonal to the plane of the substrate.


Patent
Imec | Date: 2017-09-13

The invention is related to a III-Nitride semiconductor device comprising a base substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4) so that a 2-dimensional charge carrier gas (5) is formed or can be formed near the interface between the channel layer (3) and the barrier layer (4), and at least one set of a first and second electrode (6,7) in electrical contact with the 2-dimensional charge carrier gas (5), wherein the device further comprises a mobile charge layer (MCL) (11) within the buffer layer (2) or near the interface between the buffer layer (2) and the channel layer, when the device is in the on-state. The device further comprises (3) an electrically conductive path (12) between one of the electrodes (6,7) and the mobile charge layer (11). The invention is equally related to a method for producing a device according to the invention.


Patent
Imec | Date: 2017-09-13

An interconnect structure and a method for forming it comprising the steps of:a. Providing a first entity (18a) comprising:i. a first set of line structures (8a), comprising:- a first set of conductive lines (21a),- a first set of dielectric lines (16a) made of a first dielectric material (4a) and aligned with and overlaying said first set of conductive lines (21a),ii. gaps (7) separating said line structures (8a) and filled with a second dielectric material (4b) of such a nature that said first dielectric material (4a) can be etched selectively with respect to said second dielectric material (4b);b. Providing a patterned mask (5b) on said first entity (18a);c. Etching selectively said first dielectric material (4a) through said patterned mask (5b) so as to form one or more vias (13b) in said first dielectric material (4a), andd. Removing said patterned mask (5b).

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