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Mashayekhi M.,Autonomous University of Barcelona | Llamas M.,Autonomous University of Barcelona | Carrabina J.,Autonomous University of Barcelona | Pallares J.,ICAS Group | And 2 more authors.
Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014 | Year: 2014

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): l)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library. © 2014 IEEE. Source


Llamas M.,Autonomous University of Barcelona | Mashayekhi M.,Autonomous University of Barcelona | Carrabina J.,Autonomous University of Barcelona | Pallares J.,ICAS Group | And 2 more authors.
Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014 | Year: 2014

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting. © 2014 IEEE. Source


Llamas M.,Autonomous University of Barcelona | Mashayekhi M.,Autonomous University of Barcelona | Alcalde A.,Autonomous University of Barcelona | Carrabina J.,Autonomous University of Barcelona | And 4 more authors.
IEEE/OSA Journal of Display Technology | Year: 2015

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested. © 2005-2012 IEEE. Source

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