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Schwank J.R.,Sandia National Laboratories | Shaneyfelt M.R.,Sandia National Laboratories | Dodd P.E.,Sandia National Laboratories | McMorrow D.,U.S. Navy | And 10 more authors.
IEEE Transactions on Nuclear Science | Year: 2011

The laser pulse energy thresholds for single-event upset measured by single photon and two photon absorption are measured and compared for Sandia SRAMs and DPSRAMs, and IBM 45-nm SRAMs for devices with and without the back substrate removed. These results are also compared to heavy-ion results taken on the same devices. Sandia SRAM data taken on different test dates resulted in considerably different TPA laser pulse energy thresholds even though the TPA system was calibrated using standard techniques each test date. These differences are believed to be due to changes in laser spot size. This shows that it is imperative to develop a calibration procedure that monitors all relevant laser parameters if TPA is to be used as a routine quantitative tool. Removing the back substrate makes a very large difference in TPA laser pulse energy threshold. This large difference is likely due to either displacement currents generated in the back substrate by TPA and/or nonlinear optical effects which can reduce the laser pulse irradiance in the active region. Nevertheless, the mechanism does not appear to affect the qualitative nature of TPA measurements. Both SPA and TPA laser measurements were used to estimate the heavy-ion threshold LETs of the Sandia DPSRAMs and 45-nm IBM SRAMs. Both SPA and TPA overestimated the heavy-ion threshold LET of the IBM 45-nm SRAMs (likely due to the large laser spot size compared to the size of the SRAM cell), but reasonably estimated the threshold LETs of the Sandia DPSRAMs. For the first time, TPA laser pulse energy (squared) is directly compared to SPA laser pulse energy at threshold. There is reasonable quantitative agreement between the charge required to induce upsets by TPA and SPA with the back substrate removed. © 2011 IEEE.

Sadhu B.,Ibmt Jwatson Research Center | Ferriss M.A.,Ibmt Jwatson Research Center | Natarajan A.S.,Ibmt Jwatson Research Center | Yaldiz S.,Intel Corporation | And 11 more authors.
IEEE Journal of Solid-State Circuits | Year: 2013

This paper describes a new approach to low-phase-noise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of -130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60°C temperature variation is 3 dB. At the 25 GHz center frequency, the VCOT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme. © 2013 IEEE.

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