IBM
Armonk, NY, United States
Armonk, NY, United States

The International Business Machines Corporation is an American multinational technology and consulting corporation, with headquarters in Armonk, New York, United States. IBM manufactures and markets computer hardware and software, and offers infrastructure, hosting and consulting services in areas ranging from mainframe computers to nanotechnology.The company was founded in 1911 as the Computing-Tabulating-Recording Company through a merger of the Tabulating Machine Company, the International Time Recording Company, and the Computing Scale Company. CTR was changed to "International Business Machines" in 1924, using a name which had originated with CTR's Canadian subsidiary. The acronym IBM followed. Securities analysts nicknamed the company Big Blue for its size and common use of the color in products, packaging, and logo.In 2012, Fortune ranked IBM the No. 2 largest U.S. firm in terms of number of employees , the No. 4 largest in terms of market capitalization, the No. 9 most profitable, and the No. 19 largest firm in terms of revenue. Globally, the company was ranked the No. 31 largest in terms of revenue by Forbes for 2011. Other rankings for 2011/2012 include No. 1 company for leaders , No. 1 green company in the U.S. , No. 2 best global brand , No. 2 most respected company , No. 5 most admired company , and No. 18 most innovative company .IBM has 12 research laboratories worldwide, bundled into IBM Research. As of 2013 the company held the record for most patents generated by a business for 22 consecutive years. Its employees have garnered five Nobel Prizes, six Turing Awards, ten National Medals of Technology, and five National Medals of Science. Notable company inventions include the automated teller machine , the floppy disk, the hard disk drive, the magnetic stripe card, the relational database, the Universal Product Code , the financial swap, the Fortran programming language, SABRE airline reservation system, DRAM, copper wiring in semiconductors, the silicon-on-insulator semiconductor manufacturing process, and Watson artificial intelligence.IBM has constantly evolved since its inception, acquiring properties such as Kenexa and SPSS and organizations such as PwC's consulting business , spinning off companies like printer manufacturer Lexmark , and selling off product lines like its personal computer and server businesses to Lenovo . In 2014 IBM announced that it would "offload" IBM Micro Electronics semiconductor manufacturing to Global Foundries. This transition is in progress as of early 2015. Wikipedia.


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Choi T.,IBM
Nature Nanotechnology | Year: 2017

Spin resonance provides the high-energy resolution needed to determine biological and material structures by sensing weak magnetic interactions. In recent years, there have been notable achievements in detecting and coherently controlling individual atomic-scale spin centres for sensitive local magnetometry. However, positioning the spin sensor and characterizing spin–spin interactions with sub-nanometre precision have remained outstanding challenges. Here, we use individual Fe atoms as an electron spin resonance (ESR) sensor in a scanning tunnelling microscope to measure the magnetic field emanating from nearby spins with atomic-scale precision. On artificially built assemblies of magnetic atoms (Fe and Co) on a magnesium oxide surface, we measure that the interaction energy between the ESR sensor and an adatom shows an inverse-cube distance dependence (r-3.010.04). This demonstrates that the atoms are predominantly coupled by the magnetic dipole–dipole interaction, which, according to our observations, dominates for atom separations greater than 1 nm. This dipolar sensor can determine the magnetic moments of individual adatoms with high accuracy. The achieved atomic-scale spatial resolution in remote sensing of spins may ultimately allow the structural imaging of individual magnetic molecules, nanostructures and spin-labelled biomolecules. © 2017 Nature Publishing Group


A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.


A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.


Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.


Embodiments relate to idle time accumulation in a multithreading computer system. According to one aspect, a computer system includes a configuration having a plurality of cores and an operating system (OS)-image configurable between a single thread (ST) mode and a multithreading (MT) mode in a logical partition. The MT mode supports multiple threads on shared resources per core simultaneously. The computer system also includes a multithreading facility configured to perform a method that includes executing a query instruction on an initiating core of the plurality of cores. The executing includes obtaining, by the OS-image, a maximum thread identification value indicating a current maximum thread identifier of the cores within the logical partition. The initiating core also obtains a multithreading idle time value for each of the cores indicating an aggregate amount of idle time of all threads enabled on each of the cores in the MT mode.


Patent
Ibm | Date: 2017-02-01

Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.


THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM Amultithreading computer system includesa configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.


Patent
Ibm | Date: 2017-01-18

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.


Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.


Patent
Ibm | Date: 2017-02-01

According to one aspect, a computer system includes a configuration with a machine enabled to operate in a single thread (ST) mode and a multithreading (MT) mode. In addition, the machine includes physical threads. The machine is configured to perform a method that includes issuing a start-virtual-execution (start- VE) instruction to dispatch a guest entity having multiple logical threads on the core. The guest entity includes all or a part of a guest virtual machine (VM), and issuing is performed by a host running on one of the physical threads on the core in the ST mode. The executing of the start- VE instruction by the machine includes mapping each of the logical threads to a corresponding one of the physical threads, initializing each of the mapped physical threads with a state of the corresponding logical thread, and starting execution of the guest entity on the core in MT mode.

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