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Seongnam, South Korea

Oh S.-W.,Inha University | Park H.-M.,Hyundai AUTRON | Moon Y.-H.,Inha University | Kang J.-K.,Inha University
Journal of Semiconductor Technology and Science | Year: 2013

This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a 0.13 8m CMOS technology.

Hwang J.T.,Samsung | Jung M.S.,Silicon Mitus | Kim D.H.,Samsung | Lee J.H.,Neofidelity Inc. | And 2 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

The off-the-line primary side regulation flyback LED lamp driver is proposed based on LED forward voltage tracking (VFT) and duty variation tracking (DVT) methods, which satisfy good line/load regulation, high power factor and TRIAC dimming possibility. This paper introduces that four derivative types (TYPE-I to IV) are possible to implement using supply voltage, MOSFET drain voltage and duty cycle signal with the four types of sensing circuits on the basis of VFT and DVT concepts. The load regulations of TYPE-I to IV show 0.89%, 0.51%, 0.43% and 0.56% [A/V], respectively. TYPEI to IV show ±8%, ±2%, ±2% and ±4% of line regulation over 180 to 260 V AC variation, respectively. Each type satisfies above 81% of efficiency when it delivers 6 to 12 W to the LED load at 220 VAC. The power factors of all types are above 0.9. The chip is implemented using 0.35 μm BCD process and occupies 0.76 mm2. © 1966-2012 IEEE.

Ji J.,Sungkyunkwan University | Park J.,Sungkyunkwan University | Kwon O.,Sungkyunkwan University | Chai M.,Sungkyunkwan University | And 2 more authors.
Proceedings of the Institution of Mechanical Engineers, Part D: Journal of Automobile Engineering | Year: 2014

In this paper, a macroslip detection method is proposed for a metal V-belt continuously variable transmission, and a clamping force control strategy is suggested on the basis of a macroslip detection method. Using the rotational accelerations of the primary and secondary pulleys, the velocity of the secondary pulley and the speed ratio of the continuously variable transmission variator, observation signals are defined. The characteristics of the observation signals are investigated by simulations in a vehicle-driving environment. It is found that two observation signals became unsynchronized when macroslip occurs. Considering the oscillations of the acceleration signal and the noise from the sensors or the differentiating process, a signal-processing method for the observation signals is suggested. Based on the signal-processing results, a variable called the 'amplitude difference rate' is introduced for slip evaluation. A macroslip detection method that uses the amplitude difference rate is proposed. The effectiveness of the macroslip detection method is validated by experiments. It is found from the experiments that the proposed method can effectively detect macroslip with an acceptable time delay. In addition, a clamping force control strategy based on the macroslip detection method is developed. In this strategy, the clamping force is maintained at a minimum value with a safety factor of 1 in normal driving conditions but an additional clamping force is applied when macroslip is detected. It is found from the simulation results that macroslip is eliminated by clamping force control. It is expected that the efficiency of the continuously variable transmission system can be improved by reducing the marginal clamping force using the proposed macroslip detection method and the clamping force control strategy. © IMechE 2014.

Na K.,Ulsan National Institute of Science and Technology | Jang H.,Ulsan National Institute of Science and Technology | Ma H.,Ulsan National Institute of Science and Technology | Choi Y.,Hyundai AUTRON | Bien F.,Ulsan National Institute of Science and Technology
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2015

A new all-digital impulse radio ultrawideband pulse generator in a 65-nm CMOS technology for a wireless body area network is presented. The system architecture is a delay-based pulse generator that is designed using only logic gates to minimize the power consumption. The system uses a frequency range of 3.1-4.8 GHz and 3 channels with a 500-MHz bandwidth. The maximum data rate of this system is 100 Mb/s with pulse positioned modulation and 200 Mb/s with on-off keying. Delay-based binary phase-shift keying is used to achieve an efficient spectral line characteristic. The total power consumption of the pulse generator is 30 pJ/pulse at a 1.2-V supply voltage without a static bias current. © 2015 IEEE.

Oh S.-W.,Inha University | Park H.-M.,Hyundai AUTRON | Seo J.-H.,Inha University | Jang J.-Y.,Inha University | And 2 more authors.
ISOCC 2012 - 2012 International SoC Design Conference | Year: 2012

This paper describes a spread spectrum clock generator (SSCG) circuit generating an approximate Hershey- Kiss modulation profile by dual modulators. The dual modulators consist of a slope modulator and a division modulator. The proposed scheme generates various modulation slopes to achieve a non-linear modulation profile. Since the modulators are implemented by the simple digital blocks, it can be modified upon different applications. The proposed SSCG covers output frequency of 60MHz to 200MHz with a 30KHz modulation frequency designed with a 0.11μm CMOS technology. The spread ratios and modulation positions (down, up, center) also can be controlled. © 2012 IEEE.

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