Lee D.-S.,Sungkyunkwan University |
Cho S.,Sungkyunkwan University |
Kim S.,Sungkyunkwan University |
Lee J.,Hubilon CO. |
And 5 more authors.
Analog Integrated Circuits and Signal Processing | Year: 2016
Abstract: In this paper, a low phase noise 30-GHz frequency synthesizer with a linear transconductance voltage-controlled oscillator (VCO) and dual-injection-locked frequency divider (ILFD) is presented. In order to improve the phase noise of the frequency synthesizer, the LC VCO is designed with transconductance linearization of the active devices. A dual-ILFD is proposed in order to achieve a wide locking range with low power consumption. It is implemented in 65 nm CMOS and the die area is 1.2 mm × 0.8 mm. The power consumption is 55 mW from the supply voltage of 1 V. The measured phase noise of the VCO is respectively −106 and −97.88 dBc/Hz at a 1-MHz offset from carrier frequency of 30.24 and 60.48 GHz. The measured tuning range of the VCO is about 13 %. The locking frequency range of the ILFD is from 14.1 to 45.8 GHz at the injection power of −6 dBm, with its load current being controlled automatically. © 2016 Springer Science+Business Media New York Source
Kim S.-Y.,Sungkyunkwan University |
Lee J.,Sungkyunkwan University |
Park H.-G.,Sungkyunkwan University |
Pu Y.G.,Sungkyunkwan University |
And 3 more authors.
Journal of Semiconductor Technology and Science | Year: 2015
This paper presents a 1.248 Gb/s – 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is 0.01 μs the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a 0.11 μm CMOS process, and the die area is 600 μm x 250 μm. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are 35.24 psp-p and 4.25 psrms respectively for HS-G2 mode. © 2015 Institute of Electronics Engineers of Korea. All rights reserved. Source