Huahong Grace Semiconductor Manufacturing Corporation

Shanghai, China

Huahong Grace Semiconductor Manufacturing Corporation

Shanghai, China
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Liu D.,Fudan University | Liu D.,HuaHong Grace Semiconductor Manufacturing Corporation | Duan W.,HuaHong Grace Semiconductor Manufacturing Corporation | Qian W.,HuaHong Grace Semiconductor Manufacturing Corporation
China Semiconductor Technology International Conference 2017, CSTIC 2017 | Year: 2017

This article reports a high voltage PLDMOS with 25V operating voltage and 40V breakdown voltage. Usually the PLDMOS adopts N-well as channel, and the N-well is as the drift region of NLDMOS. The PLDMOS presented in this paper adopts N-type EPI as channel, which is not affected by NLDMOS drift region. The low doping concentration of N-type EPI causes the punch through (punch through for short) in PLDMOS between the source and drain when the channel length is short than 2.5um. The PLDMOS in this paper adopts blanket phosphorus implant to suppress punch through between source and drain, and blanket boron implant to adjust threshold voltage. Without adding mask, the resulting device still has excellent characteristics under short channel length. © 2017 IEEE.


Liu D.,Fudan University | Liu D.,HuaHong Grace Semiconductor Manufacturing Corporation | Xu Z.,HuaHong Grace Semiconductor Manufacturing Corporation | Xu Z.,CAS Shanghai Institute of Microsystem and Information Technology | And 8 more authors.
China Semiconductor Technology International Conference 2017, CSTIC 2017 | Year: 2017

This article reports a high voltage DDD NMOS with 25V operating voltage and 40V breakdown voltage. Usually the DDD MOS in the logic process has a typical breakdown voltage lower than 18V. The further application requirement in higher breakdown voltage adopts LDMOS structures. In order to achieve high enough on-state breakdown voltage, the DDD NMOS presented in this paper has relatively high (about 1e13/cm2) doping level in the diffused drain region. In the case of the diffusion drain region with high level doping, the off-state breakdown voltage is affected, but the DDD NMOS in this paper adopts a novel design. Thus, the on/off-state breakdown voltage can reach 40V. The optimized device has excellent input/output characteristics and excellent on-resistance characteristics. The Ioff of the device is slightly larger and will be further optimized. © 2017 IEEE.


Cao Z.,HuaHong Grace Semiconductor Manufacturing Corporation | Kang J.,HuaHong Grace Semiconductor Manufacturing Corporation | Huang H.,HuaHong Grace Semiconductor Manufacturing Corporation | Wang H.,HuaHong Grace Semiconductor Manufacturing Corporation
China Semiconductor Technology International Conference 2017, CSTIC 2017 | Year: 2017

In this paper, water mark like defect was investigated during post clean step after W CMP. Through a series of experiments, we found this water mark defect was caused by condensed WOX residue which was dissolved into De-Ionized (DI) water at acid environment. By an additional dilute HF(DHF) wet clean step after typical W CMP process, we found that most of this defect can be removed with high efficiency to about 99.6%. © 2017 IEEE.


Xu T.,HuaHong Grace Semiconductor Manufacturing Corporation | Cao Z.,HuaHong Grace Semiconductor Manufacturing Corporation | Han G.,HuaHong Grace Semiconductor Manufacturing Corporation | Chen H.,HuaHong Grace Semiconductor Manufacturing Corporation | Wang H.,HuaHong Grace Semiconductor Manufacturing Corporation
China Semiconductor Technology International Conference 2017, CSTIC 2017 | Year: 2017

Oxygen gas is conventionally used for photoresist ashing process during the fabrication of Integrated Circuits. However, Reverse tunneling disturb fail of flash memory happened frequently if we only use Oxygen gas during photoresist ashing process after floating gate nitride etch. Through physical failure analysis, we found it is reverse word line tip that induce RTD fail. By analysis and comparison, an additional forming gas (N2H2) that can enhance polymer removal during Photo resist ashing process was introduced to solve RTD fail for flash products. © 2017 IEEE.


Fang L.,CAS Shanghai Institute of Microsystem and Information Technology | Fang L.,Huahong Grace Semiconductor Manufacturing Corporation | Fang L.,University of Chinese Academy of Sciences | Kong W.,Huahong Grace Semiconductor Manufacturing Corporation | And 4 more authors.
Journal of Semiconductors | Year: 2014

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection (SSI) and a poly-to-poly tunneling mechanism respectively. © 2014 Chinese Institute of Electronics.


Xu X.,Fudan University | Xu X.,HuaHong Grace Semiconductor Manufacturing Corporation | Huang J.,HuaHong Grace Semiconductor Manufacturing Corporation | Yu H.,HuaHong Grace Semiconductor Manufacturing Corporation | And 3 more authors.
Microelectronics Reliability | Year: 2015

This work investigates the leakage current of power LDMOS (laterally diffused metal-oxide-semiconductor) transistors with deep poly sinker, and the leakage shows a certain wafer map distribution with most of the failed dies located at the center area. It is found that the leakage current is mainly caused by the stress-induced dislocations close to the deep poly sinker. The relationship between the stress-induced dislocation (SID) and the wafer warpage is studied. Experimental results show the dislocation and the resulting leakage current can be effectively eliminated, by either modifying the device layout or optimizing the fabrication process of the poly sinker. © 2015 Elsevier Ltd. All rights reserved.


Xu X.,Fudan University | Xu X.,HuaHong Grace Semiconductor Manufacturing Corporation | Huang J.,HuaHong Grace Semiconductor Manufacturing Corporation | Yu H.,HuaHong Grace Semiconductor Manufacturing Corporation | And 7 more authors.
Journal of Semiconductors | Year: 2015

A laterally diffused metal-oxide-semiconductor (LDMOS) device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device performance under high frequency. Based upon the device design, radio-frequency (RF) LDMOS transistors for GSM (global system for mobile communication) application have been fabricated by using 0.35 μm CMOS technologies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency (PAE) is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 : 1 voltage standing wave ratio (VSWR) load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point (P10dB). The device ruggedness has been remarkably improved by using the proposed device structure. © 2015 Chinese Institute of Electronics.


Liu D.,Fudan University | Liu D.,Huahong Grace Semiconductor Manufacturing Corporation | Xu X.,Fudan University | Xu X.,Huahong Grace Semiconductor Manufacturing Corporation | And 10 more authors.
Advances in Condensed Matter Physics | Year: 2015

This paper presents a 500 V high voltage NLDMOS with breakdown voltage (VBD) improved by field plate technology. Effect of metal field plate (MFP) and polysilicon field plate (PFP) on breakdown voltage improvement of high voltage NLDMOS is studied. The coeffect of MFP and PFP on drain side has also been investigated. A 500 V NLDMOS is demonstrated with a 37 m drift length and optimized MFP and PFP design. Finally the breakdown voltage 590 V and excellent on-resistance performance (Rsp = 7.88 ohm mm2) are achieved. © 2015 Donghua Liu et al.


Xu X.,Fudan University | Xu X.,Huahong Grace Semiconductor Manufacturing Corporation | Yu H.,Huahong Grace Semiconductor Manufacturing Corporation | Huang J.,Huahong Grace Semiconductor Manufacturing Corporation | And 9 more authors.
Advances in Condensed Matter Physics | Year: 2015

A novel RF LDMOS device structure and corresponding manufacturing process are presented in this paper. Deep trench W-sinker (tungsten sinker) is employed in this technology to replace the traditional heavily doped diffusion sinker which can shrink chip size of the LDMOS transistor by more than 30% and improve power density. Furthermore, the W-sinker structure reduces the parasitic resistance and inductance and improves thermal conductivity of the device as well. Combined with the adoption of the techniques, like grounded shield, step gate oxide, LDD optimization, and so forth, an advanced technology for RF LDMOS based on conventional 0.35 m CMOS technology is well established. An F + A power amplifier product with frequency range of 1.8-2.1 GHz is developed for the application of 4G LTE base station and industry leading performance is achieved. The qualification results show that the device reliability and ruggedness can also meet requirement of the application. © 2015 Xiangming Xu et al.


Xu X.,Fudan University | Xu X.,Huahong Grace Semiconductor Manufacturing Corporation | Ci P.,Huahong Grace Semiconductor Manufacturing Corporation | Tang X.,Huahong Grace Semiconductor Manufacturing Corporation | And 6 more authors.
Advances in Condensed Matter Physics | Year: 2015

An N-type 50 V RF LDMOS with a RESURF (reduced surface field) structure of dual field plates (grounded shield, or G-shield) was investigated. The effect of the two field plates and N-drift region, including the junction depth and dopant concentration, on the DC characteristics was analyzed by employing the Taurus TCAD device simulator. A high BV (breakdown voltage) can be achieved while keeping a low R DSON (on-resistance). The simulation results show that the N-drift region dopant concentration has an obvious effect on the BV and R DSON and the junction depth affected these values less. There is an optimized length for the second field plate for a given dopant concentration of the N-drift region. Both factors should be optimized together to determine the best DC characteristics. Meanwhile, the effect of the first field plate on the BV and R DSON can be ignored. According to the simulation results, 50 V RF LDMOS with an optimized RESURF structure of a double G-shield was fabricated using 0.35 μm technologies. The measurement data show the same trend as the TCAD simulation, where a BV of 118 V and R DSON of 26 ohm·mm were achieved. © 2015 Xiangming Xu et al.

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