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Jiao S.,Samsung | Wang X.,Huada Empyrean Software Co. | Zhou M.,Samsung | Li W.,Samsung | And 6 more authors.
Optics Express | Year: 2013

In this paper, we present an efficient Computer Generated Integral Imaging (CGII) method, called multiple ray cluster rendering (MRCR). Based on the MRCR, an interactive integral imaging system is realized, which provides accurate 3D image satisfying the changeable observers' positions in real time. The MRCR method can generate all the elemental image pixels within only one rendering pass by ray reorganization of multiple ray clusters and 3D content duplication. It is compatible with various graphic contents including mesh, point cloud, and medical data. Moreover, multi-sampling method is embedded in MRCR method for acquiring anti-aliased 3D image result. To our best knowledge, the MRCR method outperforms the existing CGII methods in both the speed performance and the display quality. Experimental results show that the proposed CGII method can achieve real-time computational speed for large-scale 3D data with about 50,000 points. © 2013 Optical Society of America.

Hou L.,Beijing University of Technology | Li C.,Beijing University of Technology | Bai S.,Beijing University of Technology | Wang J.,Beijing University of Technology | And 2 more authors.
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | Year: 2013

A crosstalk-free 3D IC through silicon via (TSV) automatic placement algorithm is presented in this paper. The principle of TSV crosstalk and the effectiveness of grounded TSV shielding was proved by using Comsol. Then effectiveness of grounded TSV was quantified with a deduced formula. Power/Ground TSV and signal TSV placement algorithm has been realized, considering the impact of TSV percentage and pinch constraint on 3D IC performance. Finally, the experimental results on IBM benchmark circuits validated and verified the proposed algorithm.

Liu D.,Academy of Corps of Engineers | Ji G.,Academy of Corps of Engineers | Yan H.,Huada Empyrean Software Co.
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | Year: 2013

A placement algorithm guided by the dynamic topology of clock network is proposed for clock network optimization. During placement the clock topology is built by way of the top-down partitioning and the bottom-up clustering, moreover, it can be adjusted according to the distribution of the clock sinks; the pseudo nets are added to the bottom clusters in order to guide the distribution of the clock sinks, the clusters and pseudo nets can also be adjusted according to the distribution of the clock sinks. The experimental results show that, the clock network is greatly improved in length and power.

Huada Empyrean Software Co. and CEC Huada Electronic Design Co. | Date: 2007-10-30


Guo X.,Shanghai JiaoTong University | Wang Y.,Huada Empyrean Software Co. | Chen L.,Huada Empyrean Software Co.
Journal of the Society for Information Display | Year: 2015

A new subject-specific course on thin-film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands-on design experience. This course can be an intense 1-week course to offer a full training of design engineers in an organized way to meet the ever-increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students. © Copyright 2014 Society for Information Display.

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