Huada Empyrean Software Co.

Beijing, China

Huada Empyrean Software Co.

Beijing, China
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Yu W.,Tsinghua University | Zhao C.,Tsinghua University | Zhao C.,Shandong Yingcai University | Yang S.,Tsinghua University | Lu T.,Huada Empyrean Software Co.
Journal of the Society for Information Display | Year: 2016

Several techniques are presented for the efficient resistance calculation of wiring structures in flat panel display (FPD). The techniques are based on two-dimensional boundary element method (BEM), suitable for the geometry characteristics of the FPD structures. With an automatic strategy for boundary element partition and the analytical BEM-coupled approach, the proposed resistance solver shows good accuracy and fast computational speed. Numerical experiments demonstrate that the solver can be more than 10,000 times faster than the finite difference solver raphael while preserving good accuracy. And the proposed techniques accelerate the original BEM remarkably. Structures from real FPD designs have validated the efficiency of the proposed techniques. © Copyright 2016 Society for Information Display

Hu Q.,CAS Academy of Mathematics and Systems Science | Hu Q.,University of Chinese Academy of Sciences | Zhao L.,Huada Empyrean Software Co.
Communications in Computational Physics | Year: 2017

In this paper we are concerned with numerical methods for nonlinear time-dependent problem coupled by electron, ion and photon temperatures in two dimensions, which is called the 2D-3T heat conduction equations. We propose discontinuous Galerkin (DG) methods for the discretization of the equations. For solving the resulting discrete system, we employ two domain decomposition (DD) preconditioners, one of which is associated with the non-overlapping DDM and the other is based on DDM with small overlap. The preconditioners are constructed by dropping the couplings between particles and each preconditioner consists of three preconditioners with smaller matrix size. To gauge the efficiency of the preconditioners, we test two examples and make different settings of parameters. Numerical results show that the proposed preconditioners are very effective to the 2D-3T problem. Copyright © 2017 Global-Science Press.

Jiao S.,Samsung | Wang X.,Huada Empyrean Software Co. | Zhou M.,Samsung | Li W.,Samsung | And 6 more authors.
Optics Express | Year: 2013

In this paper, we present an efficient Computer Generated Integral Imaging (CGII) method, called multiple ray cluster rendering (MRCR). Based on the MRCR, an interactive integral imaging system is realized, which provides accurate 3D image satisfying the changeable observers' positions in real time. The MRCR method can generate all the elemental image pixels within only one rendering pass by ray reorganization of multiple ray clusters and 3D content duplication. It is compatible with various graphic contents including mesh, point cloud, and medical data. Moreover, multi-sampling method is embedded in MRCR method for acquiring anti-aliased 3D image result. To our best knowledge, the MRCR method outperforms the existing CGII methods in both the speed performance and the display quality. Experimental results show that the proposed CGII method can achieve real-time computational speed for large-scale 3D data with about 50,000 points. © 2013 Optical Society of America.

Guo X.,Shanghai JiaoTong University | Wang Y.,Huada Empyrean Software Co. | Chen L.,Huada Empyrean Software Co.
Journal of the Society for Information Display | Year: 2015

A new subject-specific course on thin-film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands-on design experience. This course can be an intense 1-week course to offer a full training of design engineers in an organized way to meet the ever-increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students. © Copyright 2014 Society for Information Display.

Li X.,Fudan University | Yang F.,Fudan University | Wu D.,Huada Empyrean Software Co. | Zhou Z.,Huada Empyrean Software Co. | Zeng X.,Fudan University
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2015

In this paper, we propose an efficient oscillation-diminishing cubic Hermite spline interpolation method for the table-based transistor model approximation. We use the cubic Hermite spline interpolation to ensure the continuity of the derivatives. Oscillation-diminishing techniques are proposed to reduce the oscillations (bumps) of interpolations such that both convergence and accuracy are significantly improved. Further, the oscillation-diminishing schemes do not rely on any real derivatives. Therefore, the proposed method can be used to build table models from measured data of the physical devices, where the real derivatives are not always available. In the proposed method, an adaptive approach is employed to generate the nonuniform interpolation grids such that the interpolation accuracy is guaranteed and the memory requirement is minimized. We also propose a novel combined exponential extrapolation method for off-state (leakage) current, which exactly follows the exponential-decay characteristic of that current. Test simulations on several classic industrial analog and mixed-signal circuits show that the proposed method can achieve high accuracy with lower computational cost compared with existing table-based model approximation methods. © 1982-2012 IEEE.

Hou L.,Beijing University of Technology | Li C.,Beijing University of Technology | Bai S.,Beijing University of Technology | Wang J.,Beijing University of Technology | And 2 more authors.
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | Year: 2013

A crosstalk-free 3D IC through silicon via (TSV) automatic placement algorithm is presented in this paper. The principle of TSV crosstalk and the effectiveness of grounded TSV shielding was proved by using Comsol. Then effectiveness of grounded TSV was quantified with a deduced formula. Power/Ground TSV and signal TSV placement algorithm has been realized, considering the impact of TSV percentage and pinch constraint on 3D IC performance. Finally, the experimental results on IBM benchmark circuits validated and verified the proposed algorithm.

Liu D.,Academy of Corps of Engineers | Ji G.,Academy of Corps of Engineers | Yan H.,Huada Empyrean Software Co.
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | Year: 2013

A placement algorithm guided by the dynamic topology of clock network is proposed for clock network optimization. During placement the clock topology is built by way of the top-down partitioning and the bottom-up clustering, moreover, it can be adjusted according to the distribution of the clock sinks; the pseudo nets are added to the bottom clusters in order to guide the distribution of the clock sinks, the clusters and pseudo nets can also be adjusted according to the distribution of the clock sinks. The experimental results show that, the clock network is greatly improved in length and power.

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