Malibu, CA, United States

HRL Laboratories
Malibu, CA, United States

HRL Laboratories , was the research arm of Hughes Aircraft. It is a dedicated research center, established in 1960, in Malibu. Currently owned by General Motors Corporation and Boeing, the research facility is housed in two large, white multi-story buildings overlooking the Pacific Ocean. Wikipedia.

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Described is system for generation of elliptic curve digital signature algorithm (ECDSA) based digital signatures. A. Secret-Share protocol is initialized between a client and a set of servers to share a set of shares of a private key s among the set of servers. The set of servers initializes a protocol to generate a digital signature on a message using the set of shares of the private key s without reconstructing or revealing the private key A. The set of servers periodically initialises a Secret-Redistribute protocol on each share of the private key A- to re- randomize the set of shares. A Secret-Open protocol is initialized to reveal the private key s to an intended recipient, wherein the private key A is used to compute the digital signature.

Described is a system for data classification using formal concept analysis (FCA). In a training phase, the system generates a FCA classification lattice, having a structure, using a set of training data. The set of training data comprises training presentations and classifications corresponding to the training presentations, in a classification phase, a set of test data having classes that are hierarchical in nature is classified using the structure of the FCA classification lattice.

A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.

A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.

Described is a system for filtering, segmenting and recognizing objects. The system receives a three-dimensional (3D) point cloud having a plurality of data points in 3D space and down-samples the 3D point cloud to generate a down- sampled 3D point cloud with reduced data points in the 3D space. A ground plane is then identified and removed, leaving above-ground data, points in the down-sampled 3D point cloud. The above-ground data points are clustered to generate a plurality of 3 D blobs, each of the 3D blobs having a cluster size. The 3D blobs are filtered based on cluster size to generate a set of 3D candidate blobs. Features are extracted from each 3D candidate blob. Finally, at least one of the 3D candidate blobs is classified as a pre-defined object class based on the extracted features.

HRL Laboratories | Date: 2017-04-26

A delta sigma modulator which has improved dynamic range. The modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the modulator processes data in the incoming analog signal in an interleaved fashion.

HRL Laboratories | Date: 2017-01-04

An active artificial magnetic conductor includes an array of unit cells, each unit cell including a top face, at least one wall coupled to the top face, a base coupled to the at least one wall, and a crossed slot in the top face. The top face, the at least one wall, and the base form a cavity and are conductive.

HRL Laboratories | Date: 2017-04-05

A metal microparticle coated with metal hydride nanoparticles is disclosed. Some variations provide a material comprising a plurality of microparticles (1 micron to 1 millimeter) containing a metal or metal alloy and coated with a plurality of nanoparticles (less than 1 micron) containing a metal hydride or metal alloy hydride. The invention eliminates non-uniform distribution of sintering aids by attaching them directly to the surface of the microparticles. No method is previously known to exist which can assemble nanoparticle metal hydrides onto the surface of a metal microparticle. Some variations provide a solid article comprising a material with a metal or metal alloy microparticles coated with metal hydride or metal alloy hydride nanoparticles, wherein the nanoparticles form continuous or periodic inclusions at or near grain boundaries within the microparticles.

A dual-polarization, circularly-polarized artificial-impedance-surface antenna has two adjacent tensor surface-wave waveguides (SWGs), a waveguide feed coupled to each of the two SWGs and a hybrid coupler having output ports, each output port of the hybrid coupler being connected to the waveguide feeds coupled to the two SWGs, the hybrid coupler, in use, combining the signals from input ports of the 90 hybrid coupler with phase shifts at its output ports.

HRL Laboratories | Date: 2017-05-03

A chip-scale scanning lidar includes a two dimensional (2D) scanning micromirror for a transmit beam and a 2D scanning micromirror for a receive beam, a laser diode and a photodetector, a first waveguide and first grating outcoupler coupled to a front facet of the laser diode, a second waveguide and a second grating outcoupler coupled to a rear facet of the laser diode on a substrate. A first fixed micromirror, a second micromirror, a third micromirror, and a focusing component are in a dielectric layer bonded to the substrate over the laser diode and photodetector. The photodetector is optically coupled to the second fixed micromirror and the third fixed micromirror for coherent detection.

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