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Yaseen S.,HKBKCE | Narayan Singh J.,HKBKCE | Tarannum S.,HKBKCE | Ahmed H.,HKBKCE | And 2 more authors.
2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings | Year: 2016

In Data Communication [1], when two or more stations send the data at the same time, there are possibilities that the data packets from different stations may collide. Thus, a protocol is required which may coordinate the data transfer among the computers that share the medium. One such MAC (Medium Access Control) Protocol uses sharing of the transmission channel using three methods namely token passing, reservation and polling. A Verilog Code is written for the same and using VLSI (Very Large Scale Integration) and System on Chip Design, Simulation Results and synthesized outputs are obtained. The results are analyzed for SPARTAN 6 FPGA devices. © 2016 IEEE.

Basthikodi M.,BIT | Ahmed W.,HKBKCE
IIOAB Journal | Year: 2016

Many-core and multi-core systems are expected to be major trends for the future decades. In this way of parallel computing, it may become great difficult to choose on which target architecture to execute a certain algorithm or application. Many core machines along with GPUs increased the extensive amount of parallelism. Some compilers are updated to emerging issues with respect to the threading and synchronization. Proper classification of algorithms and programs will benefit largely to the community of programmers to get chances for efficient parallelization. In this work we have analyzed the existing species for algorithm classification, where we discus s the classification of related work and compare the amount of problems which are difficult for classification. We have selected set of algorithms which resemble in structure for various problems but perform given specific tasks. These algorithms are tested using existing tools such as Bones compiler and A-Darwin, an automatic species extraction tool. The access patterns are produced for various algorithmic kernels by running against A-Darwin and analysis is done for various code segments. We have identified that all the algorithms cannot be classified using only existing patterns and created new set of access patterns. © 2016, Institute of Integrative Omics and Applied Biotechnology. All rights reserved.

Yaseen S.,HKBKCE | Pavithra G.,HKBKCE | Harsha K.,HKBKCE | Rehaman S.A.U.,HKBKCE | And 2 more authors.
International Journal of Applied Engineering Research | Year: 2015

This paper aims at providing the description of the proposed work to implement the advancement of infrastructure used in telecommunication for providing quality service. We discuss the components required in this like battery technology, power plants available, various kinds of float rectifiers and principle of SMPS is used, the system designed effectively provides signal for communication, various preventive measures caused in failure or malfunctioning of the devices caused in the plant are discussed in this paper. We made use of infrastructure provided by BSNL to carry out our research effectively. © Research India Publications.

Mustafa B.,BIT | Shahana R.,BIT | Ahmed W.,HKBKCE
Souvenir of the 2015 IEEE International Advance Computing Conference, IACC 2015 | Year: 2015

With the increasing proliferation of multicore processors, parallelization of applications has become a priority task. In order to take advantage of the multi-core architecture of modern processors, the legacy serial code must be analyzed to discover the regions where the parallelization effort can be more rewarding. This paper presents a parallel implementation of Doolittle Algorithm using OpenMP allowing the users to utilize the multiple cores present in the modern CPUs. The Serial Doolittle Algorithm is analyzed for computing the solution of dense system of linear equations, and is parallelized in C using the OpenMP library which makes it highly efficient, cross-platform compatible and scalable. The performance (speedup) of the Parallel Algorithm on multi-core system has been presented. The experimental results on a multi-core processor show that the proposed Parallel Doolittle Algorithm achieves good performance (speedup)compared to the sequential algorithm. © 2015 IEEE.

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