Chelmsford, MA, United States
Chelmsford, MA, United States

Time filter

Source Type

Patent
Hittite Microwave | Date: 2016-08-18

A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.


Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLLs loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.


Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLLs loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLLs feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLLs feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.


Patent
Hittite Microwave | Date: 2015-02-03

Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.


Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLLs loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal chosen from one or more reference clock signals. When the control circuit decides that the selected reference clock signal is unreliable, the control circuit disables the PLLs feedback loop and turns on the holdover switch. After the reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLLs feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.


Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLLs loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.


Patent
Hittite Microwave | Date: 2014-08-01

A microstrip combline bandpass filter includes an input port, an output port, and a plurality of resonators each including a microstrip line having a first end and a second end. One of the plurality of resonators is connected to the input port, and another of the plurality of resonators is connected to the output port. The filter also includes a plurality of pairs of series coupled varactors. The first end of each microstrip line is coupled to one of the pairs of varactors, and the second end of each microstrip line is coupled to ground.


Patent
Hittite Microwave | Date: 2014-07-18

A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase.


Patent
Hittite Microwave | Date: 2014-06-10

An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.


Patent
Hittite Microwave | Date: 2015-08-05

Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.

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