Entity

Time filter

Source Type

Chelmsford, MA, United States

Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLLs loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLLs feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLLs feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.


Patent
Hittite Microwave | Date: 2015-02-03

Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.


Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLLs loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.


Patent
Hittite Microwave | Date: 2013-03-15

A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply. A dummy amplifier is coupled to the mute amplifier and the power supply. A mute controller is coupled to the mute amplifier and the dummy amplifier, the mute controller is responsive to an enable signal and configured to enable the dummy amplifier and disable the mute amplifier when no RF output signal is being generated and disable the dummy amplifier and enable the mute amplifier when the RF output signal is being generated such that total power supply current delivered to the synthesized signal source and the dummy amplifier or mute amplifier is approximately constant before, during, and after enabling the mute amplifier to reduce phase disturbance of the RF output signals.


Patent
Hittite Microwave | Date: 2014-08-01

A microstrip combline bandpass filter includes an input port, an output port, and a plurality of resonators each including a microstrip line having a first end and a second end. One of the plurality of resonators is connected to the input port, and another of the plurality of resonators is connected to the output port. The filter also includes a plurality of pairs of series coupled varactors. The first end of each microstrip line is coupled to one of the pairs of varactors, and the second end of each microstrip line is coupled to ground.

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