Azuma T.,Hitachi Central Research Laboratory |
Azuma T.,University of Tokyo |
Kenmotsu H.,Kyushu University |
Hashidume M.,Kyushu University |
Umemura S.-I.,Tohoku University
IEEE International Ultrasonics Symposium, IUS | Year: 2011
A HIFU and imaging hybrid transducer with stacking structure for endoscopic application was described. In our previous study, a bi-laminar transducer involved an imaging and a therapeutic array transducers and a polymer layer working as an acoustic band-pass filter (ABPF) between both transducers was developed . Because the ABPF passes through the lower frequency therapeutic beam and reflects the higher frequency imaging beam, the imaging array was isolated from the therapeutic transducer. Because this prototype transducer was designed to realize ultrasound clot solution, therapeutic output was lower than that of HIFU. In this study, frequency and power optimizations are required. Based on simulation optimization, a prototype transducer consisting of a spherical HIFU transducer and a concave imaging array stacking on the HIFU transducer was fabricated. The fractional bandwidth at -20 dB of imaging pulses was 100%. The transmittance of the HIFU beam through the imaging array was 0.6. The measured bandwidth of the imaging pulse is sufficient to obtain a high resolution US image. An estimated peak intensity of HIFU beam transmitted from the prototype structure was 60% higher than that of the conventional HIFU transducer with a center hole to mount the imaging array, whose outer diameter of aperture is the same as that of the prototype structure. © 2011 IEEE.
Kawamoto T.,Hitachi Central Research Laboratory |
Suzuki M.,Renesas Electronics Corporation |
Noto T.,Renesas Electronics Corporation
Journal of Electrical and Computer Engineering | Year: 2015
A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 m CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from -5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 m and 18 mW, respectively. © 2015 Takashi Kawamoto et al.