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Krzeminski C.D.,Higher Institute of Electronics and Digital Studies
Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics | Year: 2012

Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45 nm technology nodes to improve the transistor channel mobility and the electrical performance of logic devices. For 32 and 22 nm nodes, intense research work focuses on the integration and optimization of these different techniques by accumulating the effects of different stressors. Estimating the level and the distribution of the stress field generated in the channel by the fabrication process is a complex issue. The process simulation has a key role to play in order to face the many challenges associated with the stress engineering approach in terms of scalability, yield, and design. The objective of this paper is first to evaluate the stress distribution generated by the two most usual processing steps: contact etch stop liner and embedded SiGe stressors. Next, the final stress field in nanoscale device resulting of these intentional stress sources are evaluated. Process simulation has been able to quantify the global trend observed in relatively close correlation with several experimental studies. © 2012 American Vacuum Society. Source

Barthelemy H.,CNRS Institute Materials Microelectronics nanosciences of Provence | Barthelemy H.,University of Toulon | Kussener E.,CNRS Institute Materials Microelectronics nanosciences of Provence | Kussener E.,Higher Institute of Electronics and Digital Studies | Meillere S.,CNRS Institute Materials Microelectronics nanosciences of Provence
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010 | Year: 2010

A modified Aska [1] current-mode instrumentation amplifier (IA) is proposed in this paper. The main modification consists to add of a current negative impedance converter (INIC) in order to cancel the input current offset. The proposed configuration has been simulated using typical transistor parameters of the 0.35m CMOS process from AMS [2]. Under ±1.5V supply voltage, the circuit consumes 1.65mW. The IA exhibits a sensibility of 2, 3mV per Ω. In the same simulation condition, the sensibility deviation is lower than 0.0017% in the case of a resistive sensor having an impedance variation between 990Ω and 1010Ω. © 2010 IEEE. Source

Kokosy A.,Higher Institute of Electronics and Digital Studies | Micea M.V.,Polytechnic University of Timisoara | Saey P.,Catholic University of Leuven
Proceedings - Frontiers in Education Conference, FIE | Year: 2015

Due to its high potential and encouraging results, project-based learning emerges as a highly interesting paradigm in the education systems worldwide. Moreover, robotics is an interdisciplinary field where students could learn and apply their skills in mechanics, electronics, computer science, mathematics and control engineering. This paper presents a robotics project-based learning methodology which focuses on collaborating with the industry to design, develop, evaluate, integrate and manage projects designated to be used in real-life applications. This learning method emphasizes and enables the students to apprehend the importance of fulfilling client requirements and the interactions with the client, the suppliers and with the other members of the team. The students, coached by a partner from industry, have the opportunity to apply and to improve their project management skills under a large-scale, highly complex project. This method is being applied since 2008 at ISEN Lille, France, with good results and significant impact. © 2014 IEEE. Source

Barthelemy H.,CNRS Institute Materials Microelectronics nanosciences of Provence | Bourdel S.,Aix - Marseille University | Kussener E.,Higher Institute of Electronics and Digital Studies | Vauche R.,Higher Institute of Electronics and Digital Studies
2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 | Year: 2013

A Digital CMOS BPSK modulator is presented in this paper. PSPICE simulation results of the proposed modulator are presented using BSIM3v3 transistors process parameter of the TSMC-0.18μm 1.8V CMOS technology. Between 1.6V to 1.8V supply voltage, the carrier frequency of the proposed modulator is scalable between 2.3GHz and 2.6GHz. Due to its symmetry, the proposed digital BSK modulator is fully differential. © 2013 IEEE. Source

Agency: Cordis | Branch: FP7 | Program: NOE | Phase: ICT-2007.3.1 | Award Amount: 5.46M | Year: 2008

NANOSIL Network of Excellence aims to integrate at the European level the excellent European research laboratories and capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs) and disseminate the results in a wide scientific and industrial community.NANOSIL will explore and assess the science and technological aspects of nanodevices and operational regimes relevant to n\4 technology node and beyond. It will provide a forward-look for the industry, enabling informed decisions to be taken on technology development in order to speed up technological innovation. It will encompass flagship projects on nanoscale CMOS and post-CMOS. The activities will thus be centred on the More Moore and Beyond-CMOS domains but natural links will also been established with the other ENIAC areas. Within the Network there are all the critical facilities and expertise to occupy and transcend this space. We will propose innovative concepts, technologies and device architectures- with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterisation and world leading device modelling. This work will be carried out through a network of joint processing, characterisation and modelling platforms. The consortium will work closely with and take steering from European industry. It will feed back data and know-how on materials and devices that deliver the required performance. This critical interaction will strengthen European integration in nanoelectronics, help in decision-making by industry and ensure that Europe remains at the forefront of nanoelectronics for the next 2 3 decades.

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