Hangzhou Dianzhi University

Hangzhou, China

Hangzhou Dianzhi University

Hangzhou, China

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Huang H.,Dalian University of Technology | Huang H.,Hangzhou Dianzhi University | Xu Y.,Nanjing University of Posts and Telecommunications | Wang D.,Dalian University of Technology | And 2 more authors.
ECS Transactions | Year: 2014

With the continuous scaling of CMOS technology, the doping level of N-well is constantly increasing, which leads to a big decrease in magnetic sensitivity for vertical Hall devices (VHDs). Moreover, the Gaussian profile of doping concentration gives an additional decrease in N-well effective depth, which further reduces the magnetic sensitivity. In this paper, we apply partial N-well and top p+ layer implantation techniques to lower the doping level of Nwell and improve the doping profile by means of impurity lateral diffusion and compensation effects. TCAD process and device simulations have been carried out for a typical five-contact VHD in 0.13 μm CMOS technology. Simulation results show that the current-related magnetic sensitivity is greatly improved from 40 V/AT to 110 V/AT by using the partial implantation techniques. Meanwhile, the voltage-related magnetic sensitivity is also increased and not significantly decreased. © 2014 The Electrochemical Society.


Huang H.,Dalian University of Technology | Huang H.,Hangzhou Dianzhi University | Xu Y.,Nanjing University of Posts and Telecommunications | Wang D.,Dalian University of Technology | And 3 more authors.
ECS Transactions | Year: 2014

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current- controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model's simulation results are in good agreement with the reported experimental results. © 2014 The Electrochemical Society.


Huang H.,Dalian University of Technology | Huang H.,Hangzhou Dianzhi University | Wang D.,Dalian University of Technology | Li W.,Dalian University of Technology | And 3 more authors.
Journal of Semiconductors | Year: 2012

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature. © 2012 Chinese Institute of Electronics.


Wang Y.,Beijing University of Chinese Medicine | Shu Q.,Hangzhou Dianzhi University | Wu J.-L.,Shandong University | Zhang W.,Shandong University
Journal of Combinatorial Optimization | Year: 2014

An acyclic edge coloring of a graph G is a proper edge coloring such that no bichromatic cycles are produced. The acyclic chromatic index a'(G) (G) of G is the smallest integer k such that G has an acyclic edge coloring using k colors. Fiamč ik (Math Slovaca 28:139-145, 1978) and later Alon et al. (J Graph Theory 37:157-167, 2001) conjectured that a'(G)≤ Δ +2 for any simple graph G with maximum degree Δ. In this paper, we confirm this conjecture for planar graphs without a 3 -cycle adjacent to a 6 -cycle. © 2014 Springer Science+Business Media New York.

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