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Koumboulis F.N.,Halkis Institute of Technology
IEEE International Conference on Emerging Technologies and Factory Automation, ETFA | Year: 2012

Time delay system descriptions are usually met in mechanical systems and industrial processes. Here, the general class of linear singular neutral multi delay systems is introduced. The controller is of the general proportional multi delay state feedback type. For the case of regularizable linear singular neutral multi delay systems the design problem of disturbance decoupling (DD) is solved under the constraint that the closed loop system must be left invertible. The necessary and sufficient conditions for the problem to admit a realizable solution are established and the general solution of the realizable controllers is derived. © 2012 IEEE. Source


Koumboulis F.N.,Halkis Institute of Technology
IEEE International Conference on Emerging Technologies and Factory Automation, ETFA | Year: 2013

The general class of linear singular neutral multi delay systems is introduced. The controller is of the general proportional multi delay measurement output feedback type. For the case of regularizable linear singular multi delay systems the design problem of Exact Model Matching (EMM) is solved under the assumption that the ideal model is left invertible. The necessary and sufficient conditions for the problem to admit a realizable controller solution are established and the general solution of the realizable controllers is derived. © 2013 IEEE. Source


Economakos C.,Halkis Institute of Technology | Economakos G.,National and Kapodistrian University of Athens | Koutras I.,National and Kapodistrian University of Athens
IEEE International Symposium on Industrial Electronics | Year: 2010

Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. Also, FPGAs have been traditionally suited towards fast, fixed point calculations. This paper presents an automated methodology which addresses the first problem, by using language translators and hardware behavioral or high-level synthesis. For the second problem, different approaches to support floating point operations at the behavioral domain are thoroughly investigated. Overall, an efficient methodology for design space exploration of industrial control applications is proposed, using FPGA technology. The presented experiments show that design trade-offs can be easily explored and the desired solution for each application can be efficiently selected. © 2010 IEEE. Source


Economakos C.,Halkis Institute of Technology | Economakos G.,National Technical University of Athens
Lecture Notes in Electrical Engineering | Year: 2015

In the automation industry, PLCs have been the preferred implementation platform for many decades, due to their reliability, robustness and flexibility characteristics. However, the advances of the electronics industry have always kept automation engineers busy, looking for alternative platforms, proposed for the most demanding applications. Recently, the introduction of powerful and energy efficient FPGA devices has turned their interest towards methodologies to implement PLC applications with FPGAs, in automated or semiautomated ways. This paper evaluates such a methodology, which involves a fresh and productivity boosting technology, C-based FPGA programming. As FPGAs have made hardware designs wider accepted (compared to ASICs), C-based FPGA programming promises to make them even wider accepted (compared to HDL programming), provided specific, hardware related C-level coding guidelines are followed, that can greatly improve quality of results. The proposed methodology in this paper starts form low level PLC code (IL/STL) and after a disassembly-like phase, generates C code ready for FPGA programming. Through experimentation with demanding applications that involve floating point calculations, it is shown that when proper C-level coding guidelines are followed, performance gains (faster hardware) of up to 90% can be achieved. © Springer International Publishing Switzerland 2015. Source


Koumboulis F.N.,Halkis Institute of Technology | Kouvakas N.D.,Halkis Institute of Technology
2011 19th Mediterranean Conference on Control and Automation, MED 2011 | Year: 2011

The problem of Disturbance Rejection (DR) for MIMO general neutral multi-delay systems, is studied for the case of left invertible systems with measurable disturbances. The controller used is of the dynamic type involving delays and feeding back the measurable disturbances and the plant measurement outputs. The controller is assumed to be realizable. For this system case and controller type the necessary and sufficient conditions for the problem to have a solution are established and the general analytical expression of the controller matrices solving the problem is derived. © 2011 IEEE. Source

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