Time filter

Source Type

Riyan W.,Guangzhou Runxin Information Technology Co. | Zhengping L.,Guangzhou Runxin Information Technology Co. | Jiwei H.,Fuzhou University | Jiwei H.,Nanjing Southeast University | And 3 more authors.
2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2011 | Year: 2011

A CMOS RF front-end for the Long-Term Evolution (LTE) direct conversion receiver is presented in this paper. With low noise transconductance amplifier (TCA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. Direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves 45dB conversion voltage gain, 2.7dB N F, -7dBm IIP3, and +60dBm IIP2 with calibration from 2.3GHz to 2.7GHz. The total RF front end with divider draws 40mA from a single 1.2-V supply. © 2011 IEEE.


Zhang W.,Guangzhou Runxin Information Technology Co. | Huang J.,Guangzhou Runxin Information Technology Co. | Huang J.,Nanjing Southeast University | Fang M.,Guangzhou Runxin Information Technology Co. | And 2 more authors.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

A 0.13μm CMOS Direct-Conversion WiMAX/LTE transmitter with novel binary modulation gain control scheme and wide frequency band coverage is presented. In this work, binary modulation gain control realizes 36dB gain control at baseband frequency instead of by RF VGA at RF frequency. Output power is +0.5dBm and calculated EVM is 1.8%. A 4th order Butterworth low pass filter supports 2MHz-12MHz, 7-step corner frequency control, and 30dB, -1dB/step gain control. The transmitter supports 2.3GHz-2.9GHz band. Total current consumption is 135mW with 1.2V/2.8V supply included RF DA, up-mixer, low pass filter, LO divider and buffer. ©2010 IEEE.


Wang R.,Guangzhou Runxin Information Technology Co. | Huang J.,Fuzhou University | Huang J.,Nanjing Southeast University | Li Z.,Guangzhou Runxin Information Technology Co. | And 2 more authors.
Journal of Semiconductors | Year: 2012

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. © 2012 Chinese Institute of Electronics.


Huang J.,Fuzhou University | Huang J.,Nanjing Southeast University | Wang Z.,Nanjing Southeast University | Li K.,Guangzhou Runxin Information Technology Ltd. Co. | And 2 more authors.
Journal of Semiconductors | Year: 2012

A wideband LC-tuned voltage-controlled oscillator (LC-VCO) applied in LTE PLL frequency synthesizers with constant K VCO/ω osc is described. In order to minimize the loop bandwidth variations of PLL, a varactor array is proposed, which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw (SPDT) switches to connect V tune or V DD. The switches are controlled by switching bits. With this scheme, the ratio of K V = ∂C var/∂V tune and the capacitance value of the capacitor array maintains relatively constant; furthermore, the loop bandwidth of the PLL fluctuation is suppressed. The 3.2-4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process. The VCO exhibits a maximum variation of K VCO/ω osc of only 4%. The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply. © 2012 Chinese Institute of Electronics.


Weifeng Z.,Guangzhou Runxin Information Technology Co. | Jiwei H.,Guangzhou Runxin Information Technology Co. | Jiwei H.,Fuzhou University | Riyan W.,Guangzhou Runxin Information Technology Co. | And 2 more authors.
ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems | Year: 2012

In this paper, using relative low cost 130nm RFCMOS, a high linearity, SAW-less, LTE transmitter with quadrature passive voltage mixer driven by bootstrapped 25% duty-cycle LO is presented. A tunable LC tank is added between mixer and Pre-PA amplifier (PPA). As the result, requirement on linearity of reconstruction lowpass filter (LPF), mixer and PPA are reduced. The linearity of mixer is further improved by programmable bootstrap voltages. Sideband leakage and LO Feedthrough (LOFT) can be calibrated by these bootstrap voltages. 54dB of total 84dB gain dynamic range is implemented in PPA by using binary gm cells and C-2C voltage division. 25% duty-cycle LO is generated with IQ-AND gating scheme. Delivering +1.3dBm power at 2.5GHz carrier, the transmitter achieves 46.5dB adjacent ACLR, 60.5dB LO leakage and 35.3dB sideband leakage, while consuming 127mW. The out-of-band noise is 156.2dBc/Hz at 120 MHz offset and the measured EVM is 2.4%. © 2012 IEEE.


Zhang H.B.,South China University of Technology | Zhang H.B.,University of Electronic Science and Technology of China | Cai M.,South China University of Technology | He X.,South China University of Technology | And 3 more authors.
Electronics Letters | Year: 2014

A broadband and high-K monolithic passive balun for silicon-based radio frequency integrated circuits (RFICs) are presented. It utilises the top level thick Cu metal and adopts a 16-side geometry. The proposed balun is designed and fabricated with a 0.13-μm CMOS mixedsignal 1P6M process. The measured results show that the amplitude imbalance is < 0.2 dB and the phase imbalance is within 4° from the frequency range of 0.1-7 GHz. Compared with the typical octagonal balun, the proposed design achieves the same coupling coefficients K and attains an enhancement in the transmission efficiency S 21 within the frequency range of 0.1-20 GHz, and the consumed chip area is reduced by 3%. © The Institution of Engineering and Technology 2014.


Zhang H.-B.,South China University of Technology | Zhang H.-B.,University of Electronic Science and Technology of China | Cai M.,South China University of Technology | Wu H.-J.,Guangzhou Runxin Information Technology Co. | Li Z.-P.,Guangzhou Runxin Information Technology Co.
Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China | Year: 2014

Transformer is a key device in radio frequency communication circuit, which can directly effect on the performance of the RF front-end circuit. However, there is not transformer in TSMC 0.13 m RF CMOS mixed-signal process library. In order to solve this problem, an octagonal transformer which is applied in LTE/WiMAX is designed and fabricated by the analysis of all kinds of on-chip transformer performance, and the frequency-independent lumped-element equivalent circuit model and the parameter-extracted expressions are given. The measurement results show that L and Q have excellent agreement with the measured data from the frequency range of 0.1 GHz to 10 GHz, and coupling coefficient K is perfect. The successful design of the transformer will contribute to the development and application of 4G communication chips.


Chaoxian Z.,Guangzhou Runxin Information Technology Co. | Wei W.,Guangzhou Runxin Information Technology Co. | Minhan Z.,Guangzhou Runxin Information Technology Co. | Riyan W.,Guangzhou Runxin Information Technology Co. | And 2 more authors.
Asia-Pacific Microwave Conference Proceedings, APMC | Year: 2016

This paper presents a high linearity RF receiver for S band satellite communication in 0.13um CMOS technology. An RF receiver comprises a fully differential low-noise trans-conductor amplifier (LNTA), a quadrature current mode passive mixer with 25% duty-cycle LOs, and a current-driven Active-RC complex band-pass filter/PGA which provides image rejection. The current driven mixer showing a very good 1/f noise and high-linearity performance convert an RF signal to a very low IF signal. The receiver achieves total voltage conversion gain of 105dB with 83 dB Dynamic range, 6dB noise figure, >-15dBm input-1dB compression point, +60dBm input second-order intercept point with calibration, and EVM less than 2%. The receiver dissipates 38mA from a 1.2V supply. © 2015 IEEE.


Wu H.,Guangzhou Runxin Information Technology Co. | Li B.,South China University of Technology | Zhang H.,South China University of Technology | Li Z.,Guangzhou Runxin Information Technology Co. | Zeng L.,Guangzhou Runxin Information Technology Co.
Journal of Semiconductors | Year: 2014

A single die 1.2 V multi-stage noise shaping (Mash) 2-2 delta sigma analog to digital converter (ADC) for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range (DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb (CIC) filter and two half-band filters (HBF). The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the oversampling ratio (OSR). The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm 2 and a total power of 5.2 mW. The measurement results show that the dynamic range (DR) of the proposed ADC can change from 55 to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) can get 99 dB and 86.5 dB, respectively. © 2014 Chinese Institute of Electronics.


Li W.,Guangzhou Runxin Information Technology Co. | Li W.,South China University of Technology | Chen H.,Guangzhou Runxin Information Technology Co. | Yao R.,South China University of Technology
2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010 | Year: 2010

A 5.5-GHz pulse-swallow multi-modulus frequency divider for delta-sigma fractional-N frequency synthesizers is demonstrated in this paper. The frequency divider is composed of a synchronous current mode logic (CML) divide-by-4/5 prescaler, an asynchronous CML divide-by-4 divider and a digital programmable A-M counter. The proposed divider is optimized for high frequency and low power operation; the asynchronous divide-by-4 divider is triggered by the falling edge instead of the rising edge of the synchronous divide-by-4/5 prescaler to relax the timing requirement of the feedback modulus-select signal; the feedback modulus-select signal is provided by a NOR gate instead of AND gate, and the AM counter feedback is feed at the last NOR gate in the feedback chain to minimize its delay and increase the maximum operation frequency. A prototype has been implemented in 0.35μm SiGe BiCMOS technology, occupying 0.1mm 2 active silicon areas. The operating frequency is 5.5GHz; the divide ratio is 256∼511 with step of 1; and current consumption is 6.8mA in 3V power supply. © 2010 IEEE.

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