Guangdong Womens Polytechnic College

Womens, China

Guangdong Womens Polytechnic College

Womens, China
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Cai K.,Zhongkai University of Agriculture and Engineering | Liang X.,Guangdong Womens Polytechnic College
Journal of Convergence Information Technology | Year: 2012

In this article, a fully automatic segmentation algorithm for the whole heart in cardiac computed tomography (CT) image volumes is presented. The proposed method is based on the use of an atlas label image volumes, where the desired structure is manually segmented by technical experts and double-checked by cardiologists. The three-dimensional(3D) CT images segmentation is done by registration of the reference image volumes to input images(the 3D images needing segmentation), followed by a propagation of the segmentation result from the atlas onto the input images. In the registration process, the normalized mutual information is used as an image similarity measure, while optimization is preformed using an adaptive stochastic gradient descent method. To accelerate computation time, registration was done in a multi-resolution fashion, with six resolution levels. The algorithm has been applied to the fully automated segmentation of 3D cardiac CT in volunteers. The experiment showed that the method produces accurate segmentations.


Cai K.,Zhongkai University of Agriculture and Engineering | Liang X.,Guangdong Womens Polytechnic College
International Journal of Advancements in Computing Technology | Year: 2011

Wireless Sensor Network is a new integrated technology, which combines sensor technology, wireless communication technology, Micro-Electro-Mechanical Systems technology and Digital electronic technology. Now, it has been widely used in military, industrial control, environmental monitoring, transportation, and medical. Along with the research evolution on Wireless Sensor Network, its application fields are gradually expanding. It is penetrating deep into each aspect of the human's production and life, and will be a new revolutionary technology. In this paper, a wireless acceleration node based on wireless single chip processor CC2430, an ARM7TDMI-S core based microcontroller called LPC2478 microprocessor and three-axis acceleration sensor ADXL330 is designed to monitor the mechanical system operation conditions and fault diagnosis with high efficiency. The performance and characteristics of CC2430, ADXL330 and LPC2478 are introduced compactly. The designations of hardware as well as software of wireless network node are introduced in details. The nodes perform steadily and efficiently in practical test, and it can be easily applied to other monitoring areas.


Cai K.,Zhongkai University of Agriculture and Engineering | Liang X.,Guangdong Womens Polytechnic College
Advances in Information Sciences and Service Sciences | Year: 2011

Human has always paid broad attention to body motion relating close to human health. With the development of motion biomechanics and anthropometry, people have increasingly deeply studied human body motion. The paper focuses on the measurement of body motion parameters and analysis method of body motion based on the theory of motion biomechanics. The contents involve the study on the relationship between parameters of motion biomechanics, the analysis of the law of body motion by measuring motion biomechanics parameters to provide theoretical guidance for recognition of human gesture, physical training, and so on. A system which consists of signal collection unit and data processing unit is developed to complete collection and data analysis from the motion information at wireless sensor network nodes. The experiments of motion measurement are done on the basis of performing the testing of system performance. The results show that collecting and analyzing motion information of human body by the system is a feasible method.


Liang X.,Guangdong Womens Polytechnic College
Journal of Convergence Information Technology | Year: 2012

Fingerprint authentication is becoming an important security requirement in various embedded systems. While traditional identification method, user ID plus password cannot satisfy users' needs due to various defects, they are increasingly being replaced by biometric technologies such as fingerprint, face, and voice recognition, which are known to provide higher levels of security for user authentication. In this paper, an effective wireless fingerprint authentication system is presented. We designed the wireless fingerprint authentication based on Altera's Nios II processor. The whole system design includes real-time fingerprint image collection, image preprocessing, feature extraction, matching processes, a database and wireless transmission.


Liang X.,Guangdong Womens Polytechnic College
Journal of Convergence Information Technology | Year: 2012

In modern systems, data security is needed more than ever before and many cryptographic algorithms are utilized for security services. Wireless Sensor Networks (WSN) is an example of such technologies. In this paper an innovative SOPC-based approach for the security services evaluation in WSN is proposed that addresses the issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of encryption system. The design includes a Nios II processor together with custom designed modules for the Advanced Encryption Standard (AES) which has become the default choice for various security services in numerous applications. The objective of this mechanism is to present an efficient hardware realization of AES using very high speed integrated circuit hardware description language (Verilog HDL) and expand the usability for various applications. As compared to traditional customize processor design, the mechanism provides a very broad range of cost/performance points.


Jingmin L.,Guangdong Womens Polytechnic College
International Journal of Advancements in Computing Technology | Year: 2012

A new color image segmentation algorithm of foreground and background based on Mean Shift has been proposed and implemented. The image is pre-segmentation in some areas using Mean Shift algorithm, under the MAP--MRF framework, we can get a source--sink graph about the image, and then making use of the color histogram, we can give different weights to every region. Use max-- flow algorithm to segment the weighted graph and a min--cut can be got. According to the users' inputs, some boundary can be processed by matting algorithm. The experimental results show that the method only requires less users' inputs and has a better segmentation efficiency.


Liang X.,Guangdong Womens Polytechnic College
2010 International Conference on Future Information Technology and Management Engineering, FITME 2010 | Year: 2010

With the rapid development and extensive application of computer technology, information management has become an important direction for the reform and development of office information management. The rapid development of information technology pays a solid technical foundation for office information management. Information management platform can greatly improve work efficiency and service level. Therefore, information management platform has great significance in the modern management. In view of the above, the paper made a systematic study on design and implementation of smart print information management system platform which based on a modular structure and C/S architecture. First, the paper made an overall architecture and functional design for the system based on the analysis of workflow of the print work. It introduced the achievement of specific functional modules of the C/S part. Secondly, the paper made a research on Multi-layer structure design patterns. It made a realization of a modular-based, loosely coupled, maintainability, scalability, portability and reusability smart print information management platform in light of the actual demand. Finally, the paper discussed the security of the system on aspect of authentication, data backup and exception handling. At present, the system this paper talked about has been put into use and gets good results. © 2010 IEEE.


Liang X.,Guangdong Womens Polytechnic College
Advances in Information Sciences and Service Sciences | Year: 2012

This paper presents a hardware/software (HW/SW) co-design approach using System On a Programmable Chip (SOPC) technique to achieve Joint Photographic Experts Group (JPEG) algorithm. It firstly introduces JPEG image compression technology and the system architecture. Then the hardware/software design process of JPEG encoder test bench is introduced. It focuses on using the characteristics of Field-Programmable Gate Array (FPGA) structure to achieve JPEG algorithm including the improved Discrete Cosine Transform (DCT), and Nios II embedded processor of customizable characteristics, translating image acquisition, JPEG image compression and Thin Film Transistor Liquid Crystal Display (TFT-LCD) controller into user-defined modules according to Altera Avalon bus requirements with the SOPC Builder, where the user-defined module can be added to the system under the control of soft-core Nios II Embedded. Finally, the whole system is verified on a single FPGA chip. The experimental results shows the advantages of JPEG algorithm as a FPGA hardware module includes low power consumption, high image quality, low production costs and stable performance. There's a very great practical significance to reduce costs and improve image processing speed.


Zhang L.,Guangdong Womens Polytechnic College
Applied Mechanics and Materials | Year: 2014

In the process of computer network communication, different signals subject to different communication protocols and with different signal characteristics. After invading, an entangled state which cannot be constraint formed between the signals. The characteristic differences in the polarization domain between invasion signal and communication signal is significantly reduced, and it is not easy to purify. To solve this problem, in this paper, an novel intrusion signal classification model of orthogonal polarization array is established. According to the signal loss characteristics changed by the invasion polarization, it can achieve the characteristics separation of desired signal and interference signal in the region of the polarization. the interference immunity of the separated signal is performed by a simulation analysis, it can proved that taking this vector signal processing approach not only extends the capabilities of invasion signal processing in multi-signal communications, and can significantly improve the performance of interference resistance of multi-signal network communication system. © (2014) Trans Tech Publications, Switzerland.


Liang X.,Guangdong Womens Polytechnic College
International Journal of Digital Content Technology and its Applications | Year: 2012

It is widely recognized that security in networks is still a significant challenge for researchers. A central tool for achieving system security is cryptographic algorithms which are computationally intensive. Among the various techniques found in the cryptography realm, the Rivest-Shamir-Adleman (RSA) algorithms, which is based on modular multiplications and exponentiation, has become the default standard for public key cryptography. It is computationally resource-intensive and time-consuming given a minimumally secure operand size of 1024 bits or greater. For high performance and considerable resistance to tampering attacks reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional hardware solutions, this contribution proposes an innovative system-on-a-programmable-chip (SOPC) technology which provides a compromise approach between the special-purpose application-specified integrated circuit hardware and general-purpose processors. In this paper, an information system security design for RSA algorithms evaluation is present. This proposed system was implemented into an embedded processor using a field-programmable gate array (FPGA) chip. Furthermore, the embedded RSA calculation architecture works with a reusable user IP (Intellectual Property) core library and a Nios II embedded processor in the same chip to satisfy the computational burden and feasible solution by using hardware/software co-design technique and SOPC design concept. Simulations results are conducted to show the effectiveness and merit of the proposed design method in comparison with traditional customize processor design. The performance and applicability of the proposed embedded system are exemplified by conducting several experiments on a Cyclone II development board.

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