Milpitas, CA, United States
Milpitas, CA, United States

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Patent
Grandis Inc. and Hynix Semiconductor Inc | Date: 2012-05-21

A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory.


A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.


Patent
Grandis Inc. | Date: 2011-06-03

Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.


A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer (110), a nonmagnetic spacer layer (120), and a free layer (130). The nonmagnetic spacer layer (120) is between the pinned layer (110) and the free layer (130). The free layer (130) has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer (130) is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.


Patent
Grandis Inc. | Date: 2011-01-21

A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.


Patent
Grandis Inc. | Date: 2011-01-25

Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.


Patent
Grandis Inc. | Date: 2012-03-22

A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.


Patent
Grandis Inc. | Date: 2012-04-11

A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.


A method and system for providing a magnetic junction usable (200) in a magnetic device are described. The magnetic junction includes a pinned layer (210), a nonmagnetic spacer layer (220), and a free layer (230). The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.


Patent
Grandis Inc. | Date: 2012-05-23

Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.

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