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She X.,Fudan University | Li N.,Gpix Inc. | Waileen Jensen D.,ROCK Inc.
IEEE Transactions on Nuclear Science | Year: 2012

With decreasing circuit lithography dimensions and increasing memory densities, an SEU may affect multiple adjacent memory cells. This paper presents an SEU hardened memory using error correction code that can correct single errors, double-adjacent errors, triple-adjacent errors and double-almost- adjacent errors. The proposed memory introduces small area, power and delay overheads. © 2012 IEEE.


Xuan S.,Fudan University | Li N.,GPIX Inc.
IEEE Transactions on Nuclear Science | Year: 2014

This paper presents an SEU hardened placement and routing scheme targeted at an application specific integrated circuit. The proposed scheme reduces the positive slack so that the incorrect value caused by SEU in a flip-flop is less likely to be captured by a subsequent flip-flop. Experimental results demonstrate that the proposed scheme can not only reduce the SEU susceptibility of traditional non-hardened circuits but also improve the SEU resistance of hardened circuits further. © 2014 IEEE.


Xuan S.,Fudan University | Li N.,Gpix Inc | Tong J.,Fudan University
IEEE Transactions on Nuclear Science | Year: 2013

A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU. When the clock is high, an SEU may upset the logic state of the master latch resulting in a faulty output of this flip-flop, and the erroneous value will also be locked in the slave latch when clock is low. When the clock is low, an SEU may also upset the logic state of the slave latch, resulting in a faulty output of this flip-flop. This paper presents an SEU hardened flip-flop that can mitigate SEU using an error detection circuit and a multiplexer. When the clock is high or low, an SEU in the master or slave latch of a flip-flop can be detected by the error detection circuit using dynamic logic. The multiplexer selects a correct output according to the error indication signal. The proposed flip-flop has small area, power and delay overheads and good radiation hardening capabilities. © 1963-2012 IEEE.


She X.,Fudan University | Li N.,Gpix Inc. | Tong J.,Fudan University
IEEE Transactions on Nuclear Science | Year: 2012

This paper presents an SEU hardened latch that can mitigate SEU based on an error detection circuit and a multiplexer. During the hold phase, an SEU on an internal node may upset the logic state of the latch. But the error detection circuit can detect this fault and generate fault indication signals via precharge and discharge operations. The fault indication signals control a multiplexer to select a correct output. Therefore, each latch has some error detection and correction capability. © 2012 IEEE.


She X.,Fudan University | Li N.,Gpix Inc. | Erstad D.O.,HON Inc.
IEEE Transactions on Nuclear Science | Year: 2012

This paper presents three SET tolerant dynamic logic circuits. The first one uses redundant PMOS transistors in the precharge circuit and dual redundant pull down networks in the evaluation circuit to mitigate SETs effectively. The second one adds two feedback inverters and two PMOS transistors to harden against SET, even in case of two sequential SETs. The third one connects dual redundant pull down networks in series and uses only one feedback inverter and one PMOS transistor to harden against one or two SETs. Simulation and experimental results demonstrate that these proposed schemes can achieve good SET hardening capability. © 2012 IEEE.


Xuan S.,Fudan University | Yang Y.,GPIX Inc
Proceedings - International Symposium on Quality Electronic Design, ISQED | Year: 2015

This paper presents a temperature aware dynamic thread reassignment scheme for a many-core processor. The proposed scheme uses a hardware based cluster controller to perform thermal management for each cluster of cores. The cluster controller performs dynamic thread reassignment based on the thread transfer matrix with the following methods in descending priority: reducing the hot core temperature to closest to the threshold, transferring the fewest threads, and moving threads to the cores with the fewest active neighbors. The proposed scheme can achieve both good thermal management and high performance for processor cores. © 2015 IEEE.


She X.,Fudan University | Li N.,Gpix Inc | Carlson R.M.,HON Inc | Erstad D.O.,HON Inc
IEEE Transactions on Nuclear Science | Year: 2010

Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients (SET) that come from the upstream combinational circuits and propagate to the data inputs of flip-flops near the capturing clock edge. This paper presents a SET suppressor that can mitigate such SETs. By adjusting the clock edge timing so that the flip-flop captures data when the data returns to a correct state, the SET suppressor protects a flip-flop against SETs. The clock edge timing adjustment results in flip-flop delay. However, the SET suppressor almost does not introduce flip-flop delay when no SET occurs near the capturing clock edge, which is a great majority of time. © 2010 IEEE.


She X.,Fudan University | Li N.,Gpix Inc | Farwell W.D.,RAY Company
IEEE Transactions on Nuclear Science | Year: 2010

This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses having a width less than T, where T is the longest anticipated duration of SEUs. The propose latch includes a controllable inertial delay inverter. In order to mitigate SEUs with pulse widths less than T, a global controller uses delay locked loops to control the rise and fall times of the controllable inertial delay inverter in each latch to be equal to T. This allows T to be adjustable for different applications and environmental conditions. This technique introduces little area penalty and does not adversely affect propagation delay. © 2010 IEEE.


She X.,Fudan University | Li N.,Gpix Inc.
IET Computers and Digital Techniques | Year: 2010

This study presents a single-event upset (SEU) hardened latch having first and second cross-coupled inverters and first and second programmable resistance metallisation cells. The metallisation cells may be programmed to low or high-resistance states. When set to a low-resistance state, the latch may be accessed to write a new logic state into the latch. When reset to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from getting affected by SEUs. This technique introduces little layout penalty, does not adversely affect circuit speed and is simple to implement in conventional semiconductor manufacturing process flow. © 2010 The Institution of Engineering and Technology.

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