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Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2011.3.1 | Award Amount: 4.79M | Year: 2012

Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, Beyond CMOS and advanced More-than-Moore applications, process variability and the interactions between and with electrical, thermal and mechanical effects are getting more and more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fab-ricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS. A project partner has also demonstrated how correlations can be simulated.\nWithin SUPERTHEME, the most important weaknesses which limit the use of current TCAD software to study the influence of both systematic and stochastic process variability and its interaction with electro-thermal-mechanical effects will be removed, and the study of correlations will be enabled. The project will efficiently combine the use of commercially available software and leading-edge background results of the consortium with the implementation of the key missing elements and links. It will bridge the current critical gap between variability simulation on process and device/interconnect level, and include the treatment of correlations. The capabilities of the software system will be demonstrated both on advanced analog circuits and on aggressively scaled transistors.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: Cordis | Branch: H2020 | Program: RIA | Phase: ICT-25-2015 | Award Amount: 4.54M | Year: 2016

REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are: i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost. ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits, blocks and architectures will be carefully analysed from the power-consumption point of view. In addition variability tolerant design techniques underpinned by variability analysis and statistical simulation technology will be considered. iii) Demonstration of a system on chip application using the developed memory solution and benchmarking with alternative embedded memory blocks. The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative materials. The fulfilment of the objectives above will also imply the development of: i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will allow us to improve the CMOS technology by boosting device performance. ii) New behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices. iv) Extreme low power solutions The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.


Grant
Agency: Cordis | Branch: H2020 | Program: RIA | Phase: ICT-25-2015 | Award Amount: 4.00M | Year: 2016

Our modern society has gained enormously from novel miniaturized microelectronic products with enhanced functionality at ever decreasing cost. However, as size goes down, interconnects become major bottlenecks irrespective of the application domain. CONNECT proposes innovations in novel interconnect architectures to enable future CMOS scaling by integration of metal-doped or metal-filled Carbon Nanotube (CNT) composite. To achieve the above, CONNECT aspires to develop fabrication techniques and processes to sustain reliable CNTs for on-chip interconnects. Also challenges of transferring the process into the semiconductor industry and CMOS compatibility will be addressed. CONNECT will investigate ultra-fine CNT lines and metal-CNT composite material for addressing the most imminent high power consumption and electromigration issues of current state-of-the-art copper interconnects. Demonstrators will be developed to show significantly improved electrical resistivity (up to 10Ohmcm for individual doped CNT lines), ampacity (up to 108A/cm2 for CNT bundles), thermal and electromigration properties compared to state-of-the-art approaches with conventional copper interconnects. Additionally, CONNECT will develop novel CNT interconnect architectures to explore circuit- and architecture-level performance and energy efficiency. The technologies developed in this project are key for both performance and manufacturability of scaled microelectronics. It will allow increased power density and scaling density of CMOS or CMOS extension and will also be applicable to alternative computing schemes such as neuromorphic computing. The CONNECT consortium has strong links along the value chain from fundamental research to endusers and brings together some of the best research groups in that field in Europe. The realisation of CONNECT will foster the recovery of market shares of the European electronic sector and prepare the industry for future developments of the electronic landscape


Grant
Agency: Cordis | Branch: H2020 | Program: RIA | Phase: ICT-25-2015 | Award Amount: 3.38M | Year: 2016

Among the physical limitations which challenge progress in nanoelectronics for aggressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS. SUPERAID7 will build upon the successful FP7 project SUPERTHEME which focused on advanced More-than-Moore devices, and will establish a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, including especially interconnects. This will need improved physical models and extended compact models. Device architectures addressed in the benchmarks include especially TriGate/Gate FETs and stacked nanowires, including alternative channel materials. The software developed will be benchmarked utilizing background and sideground experiments of the partner CEA. Main channels for exploitation will be software commercialization via the partner GSS and support of device architecture activities at CEA. Furthermore, an Industrial Advisory Board initially consisting of GLOBALFOUNDRIES and STMicroelectronics will contribute to the specifications and will get early access to the project results.


Patent
Gold Standard Simulations Ltd | Date: 2016-05-09

In one embodiment, a method for generating semiconductor device model parameters includes the steps:


Grant
Agency: GTR | Branch: Innovate UK | Program: | Phase: European | Award Amount: 83.64K | Year: 2015

Awaiting Public Project Summary


Patent
Gold Standard Simulations Ltd | Date: 2014-07-03

Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate channel-last process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.


Patent
Gold Standard Simulations Ltd | Date: 2016-05-09

In one embodiment, a method for generating semiconductor device model parameters includes the steps:


Variation resistant metal-oxide-semiconductor field effect transistors (MOSFETs) are manufactured using a high-K, metal-gate channel-last process. A cavity is formed between spacers formed over a well area having separate drain and source areas, and then a recess into the well area is formed. The active region is formed in the recess, comprising an optional narrow highly doped layer, essentially a buried epitaxial layer, over which a second un-doped or lightly doped layer is formed which is a channel epitaxial layer. The high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth with single or multiple delta doping, or slab doping. A high-K dielectric stack is formed over the channel epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

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