Gold Standard Simulation Ltd.

Glasgow, United Kingdom

Gold Standard Simulation Ltd.

Glasgow, United Kingdom

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Jiang X.,Peking University | Guo S.,Peking University | Wang R.,Peking University | Wang X.,University of Glasgow | And 3 more authors.
IEEE Electron Device Letters | Year: 2016

A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving metal gate granularity and line-edge roughness as the two major random variation sources. The variations of V-{\rm {th}} induced by these two major categories are theoretically decomposed based on the distinction in physical mechanisms and their influences on different electrical characteristics. The effectiveness of the proposed method is confirmed through both TCAD simulations and experimental results. This letter can provide helpful guidelines for variation-aware technology development. © 1980-2012 IEEE.


Amoroso S.M.,University of Glasgow | Compagnoni C.M.,Polytechnic of Milan | Ghetti A.,Micron Technology Inc. | Gerrer L.,University of Glasgow | And 4 more authors.
IEEE Electron Device Letters | Year: 2013

This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state. © 1980-2012 IEEE.


Amoroso S.M.,University of Glasgow | Gerrer L.,University of Glasgow | Nedjalkov M.,Vienna University of Technology | Hussin R.,University of Glasgow | And 4 more authors.
IEEE Transactions on Electron Devices | Year: 2014

This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases. © 1963-2012 IEEE.


Gerrer L.,University of Glasgow | Georgiev V.,University of Glasgow | Amoroso S.M.,Gold Standard Simulation Ltd. | Towie E.,Gold Standard Simulation Ltd. | And 2 more authors.
Microelectronics Reliability | Year: 2015

In this paper we perform trap sensitivity simulation analysis of square nanowire transistors (NWT), comparing Poisson-Schrödinger (PS) and classical solutions. Both approaches result in a very different electrostatic behaviour due to strong quantum confinement effects in ultra-scaled NWTs such as the Si NWTs presented in this work. Statistical distributions of traps are investigated, modelling the steady state impact of Random Telegraph Noise and Bias Temperature Instabilities for two crystal orientations. Statistical simulations are performed to evaluate the reliability impact on threshold voltage and ON current, emphasising the importance of both confinement and trap distribution details for the proper assessment of reliability in nanowire transistors. © 2015 Elsevier Ltd.


Gerrer L.,University of Glasgow | Georgiev V.,University of Glasgow | Amoroso S.M.,Gold Standard Simulation Ltd | Towie E.,Gold Standard Simulation Ltd | Asenov A.,University of Glasgow
Microelectronics Reliability | Year: 2015

In this paper we perform trap sensitivity simulation analysis of square nanowire transistors (NWTs), comparing Poisson-Schrödinger (PS) and classical solutions. Both approaches result in very different electrostatic behaviour due to strong quantum confinement effects in ultra-scaled NWTs such as the Si NWTs presented in this work. Statistical distributions of traps are investigated, modelling the steady state impact of Random Telegraph Noise and Bias Temperature Instabilities for two crystal orientations. Statistical simulations are performed to evaluate the reliability impact on threshold voltage and ON current, emphasising the importance of both confinement and trap distribution details for the proper assessment of reliability in nanowire transistors. © 2015 Elsevier Ltd.


Brown A.R.,Gold Standard Simulation Ltd. | Daval N.,SOITEC | Bourdelle K.K.,SOITEC | Nguyen B.-Y.,SOITEC | Asenov A.,Gold Standard Simulation Ltd.
Proceedings - IEEE International SOI Conference | Year: 2012

Variability has become a major concern, forcing the industry to consider new transistor architectures for the 22nm technology generation and below [1]. Fully depleted thin-body transistors with improved electrostatic integrity tolerate an undoped channel promising significant reduction of the random-dopant component of the statistical variability. The implementation of such transistors in future CMOS technology generations will further push the scaling limits by enabling Vdd reduction and shorter gate lengths, provided that the overall variability of these devices is effectively improved. In fully depleted architectures the electrostatic integrity and electrical characteristics are controlled by the thickness of the channel and, in the 3D case, its height and shape. The process control of these dimensions will play a critical role in the variability of the new technologies. © 2012 IEEE.


Gerrer L.,University of Glasgow | Amoroso S.M.,University of Glasgow | Hussin R.,University of Glasgow | Hussin R.,University Malaysia Perlis | And 2 more authors.
Microelectronics Reliability | Year: 2014

In this paper we investigate the sensitivity of RTN noise spectra to statistical variability alone and in combination with variability in the traps properties, such as trap level and trap activation energy. By means of 3D statistical simulation, we demonstrate the latter to be mostly responsible for noise density spectra dispersion, due to its large impact on the RTN characteristic time. As a result FinFETs devices are shown to be slightly more sensitive to RTN than FDSOI devices. In comparison bulk MOSFETs are strongly disadvantaged by the statistical variability associated with high channel doping. © 2014 Elsevier Ltd. All rights reserved.


Brown A.R.,Gold Standard Simulation Ltd. | Daval N.,SOITEC | Bourdelle K.K.,SOITEC | Nguyen B.-Y.,SOITEC | Asenov A.,Gold Standard Simulation Ltd.
IEEE Transactions on Electron Devices | Year: 2013

This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induced channel length, fin-width, and fin-height variability is carefully investigated and compared based on the threshold voltage, OFF-current, and overdrive current sensitivity. Possible improvement of the SOI substrate design for reduction of the SOI FinFET sensitivity to fin-width variation is also discussed. The individual and combined impact of the relevant statistical variability sources including random discrete dopants (RDDs), fin-line edge roughness, gate-line edge roughness, and metal gate granularity are studied and compared for the nominal 25-nm gate length FinFET designs. © 1963-2012 IEEE.


Franco J.,IMEC | Franco J.,Catholic University of Leuven | Kaczer B.,IMEC | Toledano-Luque M.,IMEC | And 8 more authors.
IEEE Electron Device Letters | Year: 2012

The measurement of the entire I D-V G characteristic of a nanoscaled pMOSFET before and after the capture of a single elementary charge in a gate-oxide defect is demonstrated. The impact of a single trapped carrier on the device characteristics is compared with 3-D atomistic device simulations. The I D-V G behavior is identified to depend on the location of the oxide defect with respect to the critical spot of the current percolation path in the channel. © 2012 IEEE.


Markov S.,University of Glasgow | Amoroso S.M.,University of Glasgow | Gerrer L.,University of Glasgow | Adamu-Lema F.,University of Glasgow | And 3 more authors.
IEEE Electron Device Letters | Year: 2013

We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits. © 1980-2012 IEEE.

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