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Dresden, Germany

GlobalFoundries is a semiconductor foundry with its headquarters located in Santa Clara, California. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices on March 2, 2009, and expanded through the acquisition of Chartered Semiconductor on January 23, 2010. The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company . On March 4, 2012, AMD announced they divested their final 14% stake in the company, which concluded AMD's multi-year plan to divest its manufacturing arm.The firm manufactures integrated circuits in high volume mostly for semiconductor companies such as AMD, Broadcom, Qualcomm, and STMicroelectronics. It has five 200 mm wafer fabrication plants in Singapore, and two 300 mm fabrication plants each in Germany and Singapore, as well as a new 300 mm fabrication plant in Malta, Saratoga County, New York in the United States scheduled to begin volume production in 2013.Sanjay Jha is the Chief Executive Officer of GlobalFoundries. Wikipedia.


A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer.


Patent
Globalfoundries and Imec | Date: 2015-01-08

The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted V band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.


Patent
Globalfoundries | Date: 2015-10-30

An electroplating apparatus includes an anode configured to electrically communicate with an electrical voltage and an electrolyte solution. A cathode module includes a cathode that is configured to electrically communicate with a ground potential and the electrolyte solution. The cathode module further includes a wafer in electrical communication with the cathode. The wafer is configured to receive metal ions from the anode in response to current flowing through the anode via electrodeposition. The electroplating apparatus further includes at least one agitating device interposed between the wafer and the anode. The agitating device is configured to apply a force to gas bubbles adhering to a surface of the wafer facing the agitating device.


Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.


Patent
Globalfoundries | Date: 2016-01-11

Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

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