Dresden, Germany
Dresden, Germany

GlobalFoundries is a semiconductor foundry with its headquarters located in Santa Clara, California. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices on March 2, 2009, and expanded through the acquisition of Chartered Semiconductor on January 23, 2010. The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company . On March 4, 2012, AMD announced they divested their final 14% stake in the company, which concluded AMD's multi-year plan to divest its manufacturing arm.The firm manufactures integrated circuits in high volume mostly for semiconductor companies such as AMD, Broadcom, Qualcomm, and STMicroelectronics. It has five 200 mm wafer fabrication plants in Singapore, and two 300 mm fabrication plants each in Germany and Singapore, as well as a new 300 mm fabrication plant in Malta, Saratoga County, New York in the United States scheduled to begin volume production in 2013.Sanjay Jha is the Chief Executive Officer of GlobalFoundries. Wikipedia.


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A method of proving inline characterization of electrical properties of a fin-shaped field effect transistor (finFET) is provided. Embodiments include applying an electrical current along a length of at least one fin of a finFET disposed over a wafer surface; generating a magnetic field across a width of the at least one fin, wherein the magnetic field is perpendicular in direction to the electrical current; and detecting electron flow concentrated at an upper portion of the at least one fin.


Patent
Globalfoundries | Date: 2016-08-04

A measurement method and system are presented for in-line measurements of one or more parameters of thin films in structures progressing on a production line. First measured data and second measured data are provided from multiple measurements sites on the thin film being measured, wherein the first measured data corresponds to first type measurements from a first selected set of a relatively small number of the measurement sites, and the second measured data corresponds to second type optical measurements from a second set of significantly higher number of the measurements sites. The first measured data is processed for determining at least one value of at least one parameter of the thin film in each of the measurement sites of said first set. Such at least one parameter value is utilized for interpreting the second measured data, thereby obtaining data indicative of distribution of values of said at least one parameter within said second set of measurement sites.


At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.


Patent
Ibm and Globalfoundries | Date: 2016-06-14

Semicondcutor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.


Patent
Globalfoundries | Date: 2016-12-06

A three-dimensional multipath inductor includes turns disposed about a center region on two layers, the turns on the two layers having corresponding geometry therebetween. Each of the turns is comprised of two or more segments that extend length-wise along the turns, and the segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A lateral cross-over is configured to couple the segments of at least one turn on one layer with the segments on a turn on a same layer to form segment paths that have a substantially same length for all segment paths in a grouping of segment paths on that same layer. A vertical cross-over is configured to couple the segments on different vertically stacked metal layers to have the segment groups with a substantially same length for all segment paths based on vertical lengths.


Patent
Ibm, Globalfoundries and STMicroelectronics | Date: 2016-11-01

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.


Patent
Ibm and Globalfoundries | Date: 2016-08-23

A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-06-2015 | Award Amount: 38.85M | Year: 2015

The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution. Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems. Developped advanced as 22nm FDSOI low power technologies with logic, analog, RF and embedded new memory components (STT RAM and RRAM) together with innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components. The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks. The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals. The project will enable an increase in Europes innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-01-2015 | Award Amount: 33.04M | Year: 2015

The REFERENCE project aims to leverage a European leading edge Radio Frequency (RF) ecosystem based on RF Silicon On Insulator (SOI) disruptive technology, perceived as the most promising to address performance, cost and integration needs for RF Front End Modules (FEMs)s. The project targets to develop over the next 3 years, innovative solutions from material, engineered substrates, process, design, metrology to system integration capable to address the unresolved 4G\ requirements for RF FEMs (data rate >1Gb/s) and pave the way to 5G. The R&D and demonstration actions include: Development of innovative RFSOI substrates for 4G\ / 5G Move to 300 mm diameter Development of 4G\ / 5G RF-SOI devices with 2 major European foundries : analog in 200 mm 130nm technology, RF digital by combining RFSOI and FDSOI in 300 mm at 22nm; Innovative design for 4G\ /5G (analog and RF digital), Integration of several 4G\ FEM components on the same chip and demonstration System in Package Technology (SiP). 3 applications are investigated : Cellular / Iot : 4G\ RFSOI FEM demonstrator at SiP device level Automotive : 4G\ RF-SOI demonstrator at SiP device level Aviation: RF-SOI high data rate wireless communication module at system level; targeting a new frequency band for aeronautic. The project is executed within 5 European countries, by on a strong and complementary and well balanced consortium, 6 large industrial companies (world leaders in material, foundries, aeronautics), 4 SMEs and a network of world class level and major European public research institutes and academics. It clearly aims to develop industrial solutions enabling European leadership and production. Through this technology disruption, REFERENCE project addresses major thrusts for smart mobility, smart society, semiconductor processes, equipments, design technology and smart systems implementation, and support the societal challenges of smart transport, as well as secure and innovative society.

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