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GlobalFoundries is a semiconductor foundry with its headquarters located in Santa Clara, California. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices on March 2, 2009, and expanded through the acquisition of Chartered Semiconductor on January 23, 2010. The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company . On March 4, 2012, AMD announced they divested their final 14% stake in the company, which concluded AMD's multi-year plan to divest its manufacturing arm.The firm manufactures integrated circuits in high volume mostly for semiconductor companies such as AMD, Broadcom, Qualcomm, and STMicroelectronics. It has five 200 mm wafer fabrication plants in Singapore, and two 300 mm fabrication plants each in Germany and Singapore, as well as a new 300 mm fabrication plant in Malta, Saratoga County, New York in the United States scheduled to begin volume production in 2013.Sanjay Jha is the Chief Executive Officer of GlobalFoundries. Wikipedia.

Chen A.,Globalfoundries
IEEE Electron Device Letters | Year: 2014

Based on probability analysis, this letter presents a simplified analytical model for the area and thickness scaling of forming voltage of resistive switching memories. The model is validated by experimental data and enables forming voltage projection. A switching resistor network model is employed to simulate the statistical distributions of forming voltage, which also confirms the analytical model. The increase of forming voltage at decreasing device area is undesirable for memory scalability. Local field enhancement may help to reduce both the magnitude of forming voltage and its area dependence. © 2013 IEEE.

Chen A.,Globalfoundries
IEEE Transactions on Electron Devices | Year: 2013

This paper presents a comprehensive crossbar array model that incorporates line resistance and nonlinear device characteristics. The model can be solved using matrix algebra and is suitable for statistical analysis. The nonlinear device solution enables the assessment of crossbar arrays with diode or nonlinear select devices. The calculation based on this model shows that voltage and current degradation due to line resistance are not negligible even for small crossbar arrays, which constrains feasible array size. Diode and nonlinear select devices significantly improve the sensing margin of reading operation and the voltage window of writing operation. This model provides a quantitative tool for accurate analysis of crossbar arrays and the evaluation of memory select devices. © 1963-2012 IEEE.

Chen A.,Globalfoundries
Applied Physics Letters | Year: 2010

Switching current control plays a critical role in the operation of resistive switching devices. Both on-state resistance and maximum reset current show strong dependence on the current limit during set switching. The dependence in unipolar switching devices can be explained by the power-driven nature of reset and dynamic competition between set and reset forces. Effective switching control improves device characteristics including uniform resistance distribution and low reset current. However, it also presents challenges for the choice of selection devices and the feasibility of unconventional architectures for resistive switching devices. © 2010 American Institute of Physics.

Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.

Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers.

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