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Isogawa T.,Toppan Photomasks Inc. | Seki K.,Toppan Photomasks Inc. | Lawliss M.,GLOBALFOUDRIES | Qi Z.J.,GLOBALFOUDRIES | And 2 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2015

A variety of repairs on EUV multilayer were conducted including protection against pattern degradation in manufactural use in order to evaluate feasibility of multilayer repair and the protection schemes. The efficacy of post-repair protection techniques are evaluated to determine the lifetime of multilayer repairs. Simulations were used to select the optimal material thicknesses for repair protection, and the simulation results are verified with the lithographic results. The results showed a high correlation coefficient. Finally, all repaired sites were cleaned multiple times to quantify repair durability and impact on wafer CD. Aerial imaging of the repair sites before and after cleans shows a dramatic degradation of wafer CD post-cleaning. However, we show that applying a surface protection material after multilayer repair successfully mitigates the influence of multilayer degradation during extensive manufacturing operations. © 2015 SPIE. Source


Zhang Z.,IBM | Koswatta S.O.,IBM | Bedell S.W.,IBM | Baraskar A.,GLOBALFOUDRIES | And 19 more authors.
IEEE Electron Device Letters | Year: 2013

Contact resistances are directly measured for contacts with sizes from 25 to 330 nm using e-beam based nano-TLM devices. Record low contact resistivities ∼1.5× 10-9 Ω · cm2 are extracted from Ni(Pt) silicide contacts on in situ boron-doped Si0.7Ge 0.3 with a chemical boron-doping density of 2× 10 21/cm3. This is very promising for pMOS applications beyond the 10-nm node. A clear dependence of contact resistance on the silicide thickness has also been found. © 1980-2012 IEEE. Source


Jeon B.,GLOBALFOUDRIES | Pal S.,GLOBALFOUDRIES | Mehta S.,GLOBALFOUDRIES | Lokesh S.,GLOBALFOUDRIES | And 4 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2013

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking). © 2013 SPIE. Source

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