Global Unichip Corporation GUC

Hsinchu, Taiwan

Global Unichip Corporation GUC

Hsinchu, Taiwan
SEARCH FILTERS
Time filter
Source Type

Hong C.-H.,National Chiao Tung University | Chiu Y.-W.,National Chiao Tung University | Zhao J.-K.,National Chiao Tung University | Jou S.-J.,National Chiao Tung University | And 2 more authors.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2015

In this paper, we present source follower PMOS Read and bit-line under-drive techniques to improve the operation speed as compared to present commercial SRAM compilers. A source follower PMOS is utilized to connect local bit-lines (LBL) to global bit-lines (GBL) instead of using a NAND gate. To further improve the discharging time from LBL to GBL, we propose a bit-line under-drive circuit to reduce the voltage level of LBL. The simulated access time of the proposed macro is 445 ps at slow N slow P (SS) corner, -40°C, 0.81 V. As compared to the SRAM macro which is generated by commercial SRAM compilers with the fastest combination, the access time of the proposed SRAM macro is 12% faster than that of commercial SRAM compilers. A 36kb high speed 6T SRAM macros with source follower PMOS Read and bit-line under-drive techniques is fabricated in 28nm HKMG CMOS process. The measurement results of the chip in SS corner show the proposed SRAM macro passes all MBIST patterns at 500 MHz at 0.81 V, room temperature. © 2015 IEEE.


Chang W.-H.,National Chiao Tung University | Chen L.-D.,National Chiao Tung University | Lin C.-H.,National Chiao Tung University | Mu S.-P.,National Chiao Tung University | And 3 more authors.
Proceedings of the International Symposium on Physical Design | Year: 2016

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and EM constraints. This paper presents a design flow to generate a PDN that can result in minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN. © 2016 ACM.


Hong C.-H.,National Chiao Tung University | Chiu Y.-W.,National Chiao Tung University | Zhao J.-K.,National Chiao Tung University | Jou S.-J.,National Chiao Tung University | And 2 more authors.
International System on Chip Conference | Year: 2014

In this paper, we propose an architecture for low power SRAM designs by using hierarchical bitlines for SRAM macros with the charge sharing Read technique. Moreover, sense amplifiers are important circuits for accessing the data from internal storage nodes to data outputs. We compare two types of sense amplifiers, a current-latched sense amplifier (CLSA) and a voltage-latched sense amplifier (VLSA), and focus on the characteristics of input offset voltages and power consumption in 28 nm HPM CMOS technology. Detailed post-layout simulations with Monte Carlo mismatch model are utilized to compare the two structures. From our analysis and implementation results, using the pass-gate based hierarchical bitline with the charge sharing Read scheme gains at least 59% and 66% LBL/GBL power reduction for a 2-bank and a 4-bank hierarchical architectures at five corners, respectively. VLSA performs lower input offset voltage, higher speed and lower power consumption as compared to CLSA. The proposed combination of the pass-gate based hierarchical bitline with the charge sharing Read scheme and VLSA is suitable for SRAM macros with the high-speed and low-power design considerations. © 2014 IEEE.


Chen S.-L.,Global Unichip Corporation GUC | Ho M.-J.,Global Unichip Corporation GUC | Sun Y.-M.,Global Unichip Corporation GUC | Lin M.W.,Global Unichip Corporation GUC | Lai J.-C.,Global Unichip Corporation GUC
Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 | Year: 2014

This paper presents an all-digital delay-locked loop with the novel digital delay line for high-speed memory interface applications. The proposed digital delay line has smaller tuning step and better tuning linearity than the prior arts. The proposed ADDLL inside the DDR3 PHY for the purpose of the 90-degree phase shift and read leveling is fabricated in a 40nm low-power CMOS process. The testchip is successfully verified at the data rate of 800∼1600Mbps. The measured peak-to-peak and rms jitter of the write DQS are 60ps and 10ps at the data rate of 1600Mbps, respectively. © 2014 IEEE.

Loading Global Unichip Corporation GUC collaborators
Loading Global Unichip Corporation GUC collaborators