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Agency: Cordis | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.

SANTA CLARA, Calif., Dec. 06, 2016 (GLOBE NEWSWIRE) -- Silvaco, Inc. today announced it has agreed to merge with Global TCAD Solutions, GTS. GTS is a TCAD specialist, based in Vienna, Austria, providing powerful and sophisticated yet efficient-to-use software for device and circuit simulation. The capabilities for advanced CMOS logic and memory, and FinFET and nanowire technologies of GTS complement Silvaco’s portfolio of 2D and 3D TCAD simulation tools and its TCAD to Spice capabilities.  The transaction is expected to be completed in January 2017. Performance and economical concerns next to reliability and yield are the key challenges for advancing semiconductors beyond 7nm.  Addressing these concerns will involve the extension of current approaches as well as the introduction of new technologies and materials. At the forefront of R&D, Path-Finding TCAD simulation allows to understand the effects and advantages of new materials and structures well before they can be physically tested on Silicon, with drastically reducing the number of costly experiments.  GTS’s Nano-Device Simulator (NDS) is a complete and fully integrated solution for true physical simulation of nano-devices at the 10/14nm and 7/5nm nodes, including profound predictive simulation for new materials and architectures to help the industry reduce time to market and development cost at the leading edge of advanced CMOS development. “GTS’s technologies are a welcome addition to Silvaco’s TCAD portfolio of tools and increases our leadership in the TCAD arena.” said Dave Dutton, CEO of Silvaco. “The acquisition also further expands our European operations in Vienna, and deepens our partnership with TU Wien, Technology University Vienna, a TCAD pioneering center.   The GTS staff deepens Silvaco’s Advanced CMOS competence which is key to our growth vision and to provide the EDA tools and solutions to help our customers innovate the highest quality and most advanced products to market. As former scientific staff of TU Wien, GTS founders and staff are actively engaged in research as well as maintaining a close relationship to the university. GTS has special expertise in quantum transport and nano-devices including models for all physical phenomena relevant for operation, performance, and reliability of nano devices, such as ballistic effects, scattering, direct tunneling, band-to-band tunneling, etc. GTS products provide valid and sound predictions of device characteristics when using novel materials and new device designs and architectures. “The combination of GTS’s expertise in physical device simulation and Silvaco’s TCAD position creates a very powerful partnership to help our customers meet the demanding development costs for advanced CMOS technologies such as FinFET, FDSOI and nanowire FET’s,” said Markus Karner,  Co-founder and CEO of GTS. “These synergies plus the ability to leverage Silvaco’s global infrastructure will help us scale out these important technologies to customers worldwide.” Silvaco, Inc. is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Silvaco delivers a full TCAD-to-signoff flow for vertical markets including: displays, power electronics, optical devices, radiation and soft error reliability and advanced CMOS process and IP development. For over 30 years, Silvaco has enabled its customers to bring superior products to market at reduced cost and in the shortest time. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia. Global TCAD Solutions is a leading TCAD provider of products and services for process and device development.  GTS offers classical TCAD as well as advanced models dedicated to study and optimize performance, variability, and reliability of n14, n7, and sub-n7 technologies. The company was founded in 2008 as a spin-off company of TU Wien (Vienna University of Technology). GTS’s mission is to bridge the gap between cutting-edge scientific developments and industrial needs in semiconductor device engineering. The company is headquartered in Vienna, Austria.

Stanojevic Z.,Vienna University of Technology | Baumgartner O.,Vienna University of Technology | Filipovic L.,Vienna University of Technology | Kosina H.,Vienna University of Technology | And 3 more authors.
Solid-State Electronics | Year: 2015

In this paper we develop several extensions to semi-classical modeling of low-field mobility, which are necessary to treat planar and non-planar channel geometries on equal footing. We advance the state-of-the-art by generalizing the Prange-Nee model for surface roughness scattering to non-planar geometries, providing a fully numerical treatment of Coulomb scattering, and formulating the Kubo-Greenwood mobility model in a consistent, dimension-independent manner. These extensions allow meaningful comparison of planar and non-planar structures alike, and open the door to evaluating emerging device concepts, such as the FinFET or the junction-less transistor, on physical grounds. © 2015 Elsevier Ltd.

Stanojevic Z.,Global TCAD Solutions GmbH. | Karner M.,Global TCAD Solutions GmbH. | Mitterbauer F.,Global TCAD Solutions GmbH. | Kernstock C.,Global TCAD Solutions GmbH.
18th International Workshop on Computational Electronics, IWCE 2015 | Year: 2015

A physically-grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrdinger-Poisson solver/mobility extractor coupled to a device simulator. It brings physical modeling of semiconductor channels to device design and engineering which until now has been the domain of TCAD tools based on purely empirical models. In this work, we specifically explore the framework components required to model devices based on III/V compound semiconductors. © 2015 IWCE.

Karner M.,Global TCAD Solutions GmbH | Stanojevic Z.,Global TCAD Solutions GmbH | Kernstock C.,Global TCAD Solutions GmbH | Cheng-Karner H.W.,Global TCAD Solutions GmbH | Baumgartner O.,Global TCAD Solutions GmbH
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | Year: 2015

A framework for FinFET design studies is presented. Our physics-based modeling approach allows to accurately capture the effects of channel cross-section, orientation and strain as well as contact resistance - for the first time all in one tool. Using this approach as a reference, the predictiveness of empirical TCAD models is extended by re-calibration. Our hierarchical tool chain is embedded in an industry-proven framework equipped with DOE and optimization modules. The capabilities are demonstrated in a simulation study on a recent FinFET technology node. © 2015 IEEE.

Kernstock C.,Global TCAD Solutions GmbH | Stanojevic Z.,Global TCAD Solutions GmbH | Baumgartner O.,Global TCAD Solutions GmbH | Karner M.,Global TCAD Solutions GmbH
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | Year: 2015

In this work, a fully automated process emulation is presented. Starting from industrial standard gdsII mask files a user friendly and fast way to create TCAD ready models has been realized. A three step approach is used. The creation of virtual layers to allow for logical operation based on masks is shown. Then the geometrical and dopant profile instantiation is carried out. Third the mesh generation based on and optimized on the information of the first two steps is shown. Industry-relevant sample applications for the implemented work-flow ranging from a radiation hardened latch to a state of the art FinFET SRAM cell are demonstrated. © 2015 IEEE.

Demel H.,Global TCAD Solutions GmbH | Stanojevic Z.,Global TCAD Solutions GmbH | Karner M.,Global TCAD Solutions GmbH | Rzepa G.,Vienna University of Technology | Grasser T.,Vienna University of Technology
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | Year: 2015

In this work, the distribution, execution and performance of TCAD simulations on grid and cloud systems are investigated. A module for distributed computing which can uniformly interface both grid and cloud computing systems has been implemented within GTS Framework. Automated allocation of resources for user jobs on a combined platform has been achieved. Traditional grid-computing systems are compared with cloud-based systems. Strategies for cost-effective allocation of cloud-resources are presented. The performance of a typical TCAD application run on a grid, in the cloud, and a hybrid system combining both are assessed. © 2015 IEEE.

Baumgartner O.,Vienna University of Technology | Stanojevic Z.,Vienna University of Technology | Schnass K.,Global TCAD Solutions GmbH | Karner M.,Global TCAD Solutions GmbH | Kosina H.,Vienna University of Technology
Journal of Computational Electronics | Year: 2013

The Vienna Schrödinger-Poisson (VSP) simulation framework for quantum-electronic engineering applications is presented. It is an extensive software tool that includes models for band structure calculation, self-consistent carrier concentrations including strain, mobility, and transport in transistors and heterostructure devices. The basic physical models are described. Through flexible combination of basic models sophisticated simulation setups for particular problems are feasible. The numerical tools, methods and libraries are presented. A layered software design allows VSP's existing components such as models and solvers to be combined in a multitude of ways, and new components to be added easily. The design principles of the software are explained. Software abstraction is divided into the data, modeling and algebraic level resulting in a flexible physical modeling tool. The simulator's capabilities are demonstrated with real-world simulation examples of tri-gate and nanoscale planar transistors, quantum dots, resonant tunneling diodes, and quantum cascade detectors. © 2013 Springer Science+Business Media New York.

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2013.3.1 | Award Amount: 4.16M | Year: 2014

While feature sizes are continuously scaled towards atomic dimensions, industry is increasingly confronted with unexpected physical artefacts to be considered at each new technology node. Among these, process variation and parameter degradation lead to reliability concerns impacting integrated circuit design at all abstraction levels. As variation and degradation may become a limiting factor for future scaled technologies, there has been a tremendous research effort in understanding these artefacts. Versatile tools, allowing consideration of these artefacts and their combined impact during the design of ICs are still in their infancy. Rather than developing yet another design support methodology, we aim to combine and refine existing reliability and variability prediction methodologies at the abstraction layers with highest industrial importance: Register transfer (RT) level - usual design entry, gate level where most design for reliability (DfR) techniques are applied, and transistor level - where final sign-off is made.MoRV will cover the strong relationship between variability and ageing, which are usually treated separately, fostering the idea of treating ageing as a form of time-dependent variability. Combined models from transistor, over gate, to RT level will be characterized directly from silicon measurement and all models will be able to interpret the same characterization data base from the silicon measurement.The results will be introduced into a reference design flow combined with a multi-level multi-physics engine. Final goal of MoRV is to enable automated synthesis from specification to circuit. Each model layer will offer reliability and variation prediction for typical and worst case scenarios in order to assess the effectiveness of available design techniques.

Stanojevic Z.,Vienna University of Technology | Karner M.,Global TCAD Solutions GmbH | Kosina H.,Vienna University of Technology
Technical Digest - International Electron Devices Meeting, IEDM | Year: 2013

We conduct a comprehensive simulation study of non-planar n-type channels based on consistent, physical models containing measurable quantities rather than fit-parameters. This contrasts empirical thin-body models used in classical/quantum-corrected TCAD. The method involves the self-consistent solution of the two-dimensional Schrödinger-Poisson system, combined with linearized Boltzmann transport in the third dimension. We advance the art of simulation by (i) introducing quantum simulation on unstructured meshes for arbitrary geometries, (ii) providing an efficient framework for rapid evaluation of device designs, and (iii) contributing a surface roughness scattering model for arbitrarily shaped surfaces. Consistent modeling allows us to make reliable assertions with respect to device performance. © 2013 IEEE.

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