Ding Y.,National University of Singapore |
Cheng R.,National University of Singapore |
Du A.,Global Foundries Singapore Pte. Ltd. |
Yeo Y.-C.,National University of Singapore
Journal of Applied Physics | Year: 2013
The local strain components in the source/drain (S/D) and channel regions of Si fin field-effect transistor (FinFET) structures wrapped around by a Ge2Sb2Te5 liner stressor were investigated for the first time using nano-beam diffraction. When the Ge2Sb 2Te5 (GST) layer changes phase from amorphous to crystalline, it contracts and exerts a large stress on the Si fins. This results in large compressive strain in the S/D region of 1 ̄10-oriented Si FinFETs of up to -1.15% and -1.57% in the 110 (horizontal) and 001 (vertical) directions, respectively. In the channel region of the FinFETs under the metal gate, the GST contraction results in up to -1.47% and -0.61% compressive strain in the 110 and 001 directions, respectively. In the channel region, the 110 compressive strain is higher at the fin sidewalls and lower near the fin center, while the 001 compressive strain is lower at the sidewalls and higher near the center. © 2013 American Institute of Physics.
Weerasekera R.,Agency for Science, Technology and Research Singapore |
Li H.Y.,Agency for Science, Technology and Research Singapore |
Yi L.W.,Agency for Science, Technology and Research Singapore |
Sanming H.,Agency for Science, Technology and Research Singapore |
And 3 more authors.
IEEE Electron Device Letters | Year: 2013
Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling. © 2012 IEEE.
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-03-01
An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-06-04
An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor.
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2012-08-16
A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.