Global Foundries Singapore Pte. Ltd.

Singapore, Singapore

Global Foundries Singapore Pte. Ltd.

Singapore, Singapore
SEARCH FILTERS
Time filter
Source Type

Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-07-31

Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.


Patent
Global Foundries Singapore Pte Ltd. and Freescale Semiconductor | Date: 2011-09-29

A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-07-25

A polishing pad, an apparatus for chemical mechanical polishing of semiconductor wafers and a method of making a device using the same are presented. The apparatus includes a first platform for mounting a semiconductor wafer; a second platform for mounting a polishing pad; a rotator for rotating the wafer against the polishing pad; and a diamond dresser for dressing the polishing pad. The polishing pad has a single groove of a width (w) surrounding the periphery of an undressed portion of the polishing pad thus eliminating contact of the undressed portion with the outer edge of the diamond dresser.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2014-12-29

Integrated circuits and methods fabricating memory cells and integrated circuits are provided. In one embodiment, a method for fabricating a memory cell includes doping a semiconductor substrate to define a conductive region. The method includes forming a stacked structure over the semiconductor substrate. The stacked structure lies over the conductive region and includes a control gate overlying a floating gate. A source line region is formed adjacent a first side of the stacked structure. The method includes forming a contact over the semiconductor substrate and adjacent a second side of the stacked structure to define an electrical current path from the source line region through the conductive region under the stacked structure to the contact.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2012-08-16

A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-06-04

An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor.


Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes producing an interposer with an insulation plate and a plurality of through vias passing through the insulation plate. The interposer has a prime area and an in prime area. A prime area test circuit is formed in the prime area, where the prime area test circuit includes a portion of the plurality of through vias that are electrically connected in series.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2013-03-01

An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2014-02-06

A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.


Patent
GLOBAL FOUNDRIES Singapore Pte. Ltd. | Date: 2014-03-10

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.

Loading Global Foundries Singapore Pte. Ltd. collaborators
Loading Global Foundries Singapore Pte. Ltd. collaborators