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Wang P.,Norwegian University of Science and Technology | Ytterdal T.,Norwegian University of Science and Technology | Halvorsrod T.,GE Vingmed Ultrasound AS
2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings | Year: 2013

A low noise single-ended to differential linear switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (fs) 26-MHz ultrasound imaging. To fit the higher source impedance from gradually scaled piezo-electric transducers (PZT) in ultrasound imaging systems, a charge sampling amplifier with a fixed integration time as the first stage exhibits the lower noise, and higher sensitivity compared to the conventional voltage sampling amplifiers. The second voltage sampling stage converts the single-ended input to differential outputs with an exponential gain control which exploits an 8b binary capacitor (CAP) array, and the gain varies dB-in-linear from -14dB to 14dB. To reduce the capacitance spread for a binary-weighted 8b CAP array, the array is segmented between the upper 4b and lower 4b by a divider capacitor. Simulation results show the analog part of proposed amplifier consumes 1.25mA at 1.8V, has HD2 -62dB, HD3 -79dB at 150mV output Vpp, and the input referred noise (IRN) is 6.56pA/√Hz at 4MHz and 25.3nArms at a sampling frequency (fs) of 30MHz. The layout size is 310μm×370μm. © 2013 TU Dresden. Source


Wang P.,Norwegian University of Science and Technology | Ytterdal T.,Norwegian University of Science and Technology | Halvorsrod T.,GE Vingmed Ultrasound AS
2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings | Year: 2013

A low noise single-ended to differential linear two-stage switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (fc) ultrasound imaging. To simplify the clock generator and improve linearity, the voltage sampling technique is adopted to replace the charge sampling for sake of the source impedance of piezo-electric transducers (PZT) not being as high as capacitive micro-machined ultrasonic transducers (CMUT) in ultrasound imaging systems. The two-stage VGA based on a single-stage OTA in each stage to save the power, and controlled by the 10-bit digital signals, has the maximum dB-in-linear gain varied from -14dB to 32dB. The first stage converts the single-ended input to differential outputs with a 2-bit 6dB/step coarse gain control varying from 0dB to 18dB, and the second stage has a fine gain control which exploits an 8b binary capacitor (CAP) array varying from -14dB to 14dB. For reducing the capacitance spread for a binary-weighted 8b (1:256) CAP array, the array is divided between the upper 4b and lower 4b by a divider capacitor. Simulation results show the core analog part of two-stage VGA consumes 900μA at 1.8V, has HD2 -61dB, HD3 -77dB at 190mV output Vpp, and the input referred noise (IRN) is √ at 4MHz at the maximum gain and a sampling frequency (fs) of 30MHz. The layout size is 387μm×502μm. © 2013 TU Dresden. Source


Wang P.,Norwegian University of Science and Technology | Halvorsrod T.M.,GE Vingmed Ultrasound AS | Ytterdal T.,Norwegian University of Science and Technology
Electronics Letters | Year: 2014

An inverter-based ultra-low-power, low-noise, single-ended to differential continuous-time variable gain amplifier is presented for 2-6 MHz second harmonic cardiac imaging ultrasound probes in a 65 nm CMOS technology. The proposed variable gain amplifier (VGA) consists of three equal inverters and resistor arrays which form a feedback loop. To improve both the power and noise performances, the inverters operate in the sub-threshold region by adopting a 0.5 V supply voltage. By doubling the input transconductance of the VGA, the noise figure (NF) is enhanced further. The 6-b thermometer resistor arrays achieve a gain range of the VGA from 0 to 22 dB. The total power consumption is 55 μW, NF is 2.7 dB referred to an 8 kΩ source resistor at a centre frequency of 4 MHz. 8-b thermometer calibration codes are added into the inverters to force the static operating point of the inverters to half of the supply voltage, which could increase the immunity of the second harmonic distortion (HD2) to the process variation. The HD2 of the proposed VGA is -60.6 dB at the 330 mV peak-to-peak output swing. The active size is 154 × 102 μm. © The Institution of Engineering and Technology 2014. Source


Wang P.,Norwegian University of Science and Technology | Ytterdal T.,Norwegian University of Science and Technology | Halvorsrod T.M.,GE Vingmed Ultrasound AS
2013 IEEE Biomedical Circuits and Systems Conference, BioCAS 2013 | Year: 2013

Since the new generation of ultrasound imaging probes will integrate thousands of receive and transmit channels into a single probe, the power, noise, and chip cost become the top challenges for the analog front end of ultrasound imaging probes. This paper investigates a low-power, low-noise, and low-cost single-end-ed to differential variable gain amplifier (VGA) for 2-6-MHz second harmonic imaging ultrasound probes in a 0.18μm CMOS technology. The proposed VGA has two stages. The first stage is an inverter-based voltage sampling switched-capacitor VGA (SC-VGA) with a 6b binary-weighted gain control, and the second stage is a 4b thermometer continuous-time amplifier with tunable gain that implements the single-end to differential conversion. Power consumption and noise are highly improved by adopting an inverter to replace the operational trans-conductance amplifier (OTA) that is commonly employed in traditional SC-VGAs. Flicker noise and DC offset are canceled out by using an auto-zeroing technique. While the small layout size is achieved not only by adopting a dividing capacitor which separates the 6b binary-weighted capacitor (CAP) array between the upper 3b and lower 3b to decrease the capacitance spread in the first stage, but also by employing a common-source amplifier as a single-ended to differential converter instead of the SC-amplifier to avoid the CAP arrays. The proposed VGA has a total gain range from -9dB to 22dB. The power consumption for the core analog circuitry is 140μA at 1V supply voltage. The input referred noise is 8nV/√Hz at the center frequency of 4MHz, and the second harmonic distortion (HD2) is -61dB at a 400mV peak to peak output swing with a 30MHz sampling frequency. The layout size is 109μm×164μm. © 2013 IEEE. Source


Wang P.,Norwegian University of Science and Technology | Ytterdal T.,Norwegian University of Science and Technology | Halvorsrod T.M.,GE Vingmed Ultrasound AS
2015 European Conference on Circuit Theory and Design, ECCTD 2015 | Year: 2015

This paper proposes two surfing architectures of the front-end for cardiac ultrasound imaging systems by removing the high voltage (HV) transmitter/receiver (Tx/Rx) switch in traditional ultrasound imaging systems, and connecting the input and the local ground of the Rx to the output of the Tx directly. Both advantages and challenges are presented. During the emitting phase, the Rx is on reset mode and voltages at all internal nodes in the Rx will follow the transmitting pulse, and this phenomenon exhibits the Rx is in the surf as the transmitting pulse. By removing the Tx/Rx switch, the Rx can avoid saturating status during the pulse emitting phase in Tx, and can receive the reflected echo signals in an efficient way after the emitting phase. While the input of the Rx connecting to the PZT transducer directly without the Tx/Rx switch, the received echo signals will not be distorted by the Tx/Rx switch, and the switched-capacitor (SC) front-end of the Rx can be relaxed in the design. Currently the bulk CMOS technology may not support this architecture because of its intrinsic process limitation and relatively large parasitic capacitance of the PN junctions. SOI CMOS technology could be a feasible CMOS technology because its parasitic capacitance of the PN junction is much smaller and its process is different from the bulk CMOS technology. The simulation is based on an inverter-based SC amplifier in a high voltage 0.18 μm 50 V/1.8 V bulk CMOS technology, and a HV switch is based on a model which cannot be implemented in a bulk CMOS technology. © 2015 IEEE. Source

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