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Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,Gamesa Innovation and Technology | Guerrero J.M.,University of Aalborg
IEEE Transactions on Power Electronics | Year: 2013

A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/ limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions. © 1986-2012 IEEE.

Golestan S.,Islamic Azad University at Abadan | Ramezani M.,Islamic Azad University at Abadan | Guerrero J.M.,University of Aalborg | Freijedo F.D.,Gamesa Innovation and Technology | Monfared M.,Ferdowsi University of Mashhad
IEEE Transactions on Power Electronics | Year: 2014

The phase-locked loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge that is associated with the PLLs is how to precisely and fast estimate the phase and frequency, when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. An MAF is a linear-phase finite-impulse-response filter, which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loop filter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations. © 2013 IEEE.

March V.,Gamesa Innovation and Technology
IET Seminar Digest | Year: 2015

The paper presents an analysis of lightning activity in 18 wind farms located at the north of Spain based on the information from LLS during 4 years. Total number of flashes attached by wind turbines and statistical information of the peak currents to the wind turbines are obtained based on hypothesis from previous field observations. Data derived from LLS is also compared with methodology described in IEC standard and with a methodology developed by Gamesa to estimate the total number of flashes attaching to wind turbines in a wind farm. Results in this paper confirm that current IEC Method underestimates the number of direct lightning flashes to wind turbines and that a new methodology may be developed to reduce the error and uncertainty of the results. © 2015, Institution of Engineering and Technology. All rights reserved.

Malvar J.,University of Vigo | Lopez O.,University of Vigo | Yepes A.G.,University of Vigo | Vidal A.,University of Vigo | And 3 more authors.
IEEE Transactions on Industrial Electronics | Year: 2014

The use of multiphase motor drives is an increasingly important strategy nowadays. These multiphase machines are usually modeled by a reference frame transformation to avoid the cross-coupling of variables. This transformation decomposes the original n-dimensional vector space into orthogonal subspaces. Mapping the voltage and current harmonics into the subspaces in distributed machines is important because it allows to identify which components are related to the torque and which ones just increase the machine losses. The sequence identification of each harmonic is also important in closed-loop current harmonic compensation to set the controllers. In addition, the harmonic mapping is interesting in multimotor systems to know how harmonics from one machine can affect the other machines in the system. In this paper, a simple graphical method for time harmonic subspace and sequence identification is proposed. This method is valid for symmetrical machines of any phase number n, it provides full subspace and sequence identification and it can be used in multimotor systems. Experimental results using a five- and a six-phase motor in single-drive configuration and a series-connected two-motor six-phase drive validate the proposed method. © 1982-2012 IEEE.

Golestan S.,Islamic Azad University at Abadan | Monfared M.,Ferdowsi University of Mashhad | Freijedo F.D.,Gamesa Innovation and Technology | Guerrero J.M.,University of Aalborg | Guerrero J.M.,University of Barcelona
IEEE Transactions on Industrial Electronics | Year: 2014

Control Parameters design of a three-phase synchronous reference frame phase locked loop (SRF-PLL) with a prefiltering stage (acting as the sequence separator) is not a trivial task. The conventional way to deal with this problem is to neglect the interaction between the SRF-PLL and prefiltering stage, and treat them as two separate systems. This approach, although very simple, is not optimum as the prefiltering stage and the SRF-PLL may have comparable dynamics. The aim of this paper is to develop a systematic and efficient approach to design the control parameters of the SRF-PLL with prefiltering stage. To this end, the paper first optimizes the performance of the prefiltering stage in detection of the sequence components. The paper then proceeds to reduce the interaction between the prefiltering stage and SRF-PLL, which is achieved by employing a derivative-filtered proportional-integral-derivative controller as the loop filter (instead of the commonly adopted proportional-integral controller) and arranging a pole-zero cancellation. The suggested method is simple and efficient, and is applicable to the joint operation of different sequence separation techniques and the SRF-PLL. The effectiveness of the suggested design approach is confirmed through extensive experimental results. © 1982-2012 IEEE.

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