Time filter

Source Type

Reddy G.V.S.,G Pulla Reddy Engineering College
International Journal of Electrical Power and Energy Systems | Year: 2016

Saving of fuel cost can be done through proper commitment of available generating units. This paper presents a novel technique to solve the problem of unit commitment through sorting of units into different clusters based on Imperialistic Competition Algorithm (ICA). This sorting is implemented in order to decrease the overall operating cost and to assure the various constraints that involve minimum up/down. The technique of unit commitment is a significant assignment in the normal working of power systems which can actually be represented as a large scale minimization problem that involves non linear mixed integers. A new technique employing the concept of cluster algorithm called as additive and divisive hierarchical clustering has been used based on a new technique called as Imperialistic Competition Algorithm in order to carry out the technique of unit commitment. Proposed methodology involves two individual algorithms. Additive cluster algorithm has been employed while the load is increasing while divisive cluster algorithm has been used when the load is decreasing. The technique that has been developed has been tested on system with generating units in range of 10-100 and the superior performance of the technique has been reported through simulation results. © 2016 Elsevier Ltd. All rights reserved.


Chakradhar K.V.P.,G Pulla Reddy Engineering College | Subbaiah K.V.,Andhra University | Kumar M.A.,St Mark Educational Institution Society Group Of Institutions | Reddy G.R.,Sri Krishnadevaraya University
Polymer - Plastics Technology and Engineering | Year: 2012

The inter-cross-linked networks of unsaturated polyester (UP) toughened epoxy blends were developed. Montmorillonite (MMT) clay was dispersed into the same system to prepare blended epoxy/UP/clay nanocomposites in different weight ratios viz. 0%, 1%, 2%, 3% and 5%. Mechanical properties like tensile strength (TS), impact strength (IS) and interlaminar shear strength (ILSS) were characterized for the above nanocomposites. Blended nanocomposites were fabricated by high shear mechanical mixing followed by ultra-sonication process to get homogeneous mixing under the aid of in situ polymerization. Mechanical properties were studied as per ASTM standards. Data obtained from mechanical property studies indicated that the introduction of UP into epoxy resin improved the impact strength to an appreciable extent. Impact strength (IS) and tensile strength (TS) were significantly improved and optimized at 3 wt. % clay content when compared with neat blend (0 wt. % clay) composites. The homogeneous morphologies of the UP toughened epoxy and epoxy/UP/clay nanocomposite systems were ascertained using scanning electron microscope (SEM) studies. © 2012 Copyright Taylor and Francis Group, LLC.


Vijaya Kumar G.,G Pulla Reddy Engineering College | Shoba Bindu C.,Jawaharlal Nehru University
Advances in Intelligent Systems and Computing | Year: 2016

IEEE 802.11-based wireless mesh networks (WMNs) are emerging as the promising technology to provide last-mile broadband Internet access. A WMN is composed of mesh clients (MCs) and mesh access points (MAPs). A mesh client has to associate with one of the MAPs in order to access the network. Since the client performance depends on the selected MAP, how to select a best MAP is an open research problem. The traditional association mechanism used in WLAN, is based on received signal strength (RSS) which received criticism in the literature as it does not consider many important factors such as access point load, channel conditions, medium contention, etc. This paper proposes a novel scheme of MAP selection in WMNs. The basic idea is to reduce the negative impact of low throughput clients over high throughput clients. The performance of our scheme is evaluated through simulations and we show that our scheme performs better than RSS-based association scheme. © Springer India 2016.


Reddy G.K.,G Pulla Reddy Engineering College | Achari K.L.,G Pulla Reddy Engineering College
Proceedings of 2015 IEEE 9th International Conference on Intelligent Systems and Control, ISCO 2015 | Year: 2015

In this paper, we presented the novel design and development of a non-invasive new integrated device for measuring calories burnt from the heart rate in Arduino environment. By using the heart rate, a relation for calories burnt will be calculated. As obese people are most concerned about losing their weight, they regularly need to check the weight they lose during exercises. This calorie estimator helps in calculating calories burnt by using raise in heartbeat during am exercise. In this project, heart rate is measured using Heartbeat sensor (IR sensor). However, most heart rate measuring tools and environments are expensive and do not follow ergonomics. Our proposed IR sensor is economical and user friendly and uses optical technology to detect the flow of blood through index finger. In this project, Arduino is used in which microcontroller ATmega328 is embedded into it, suitable codes have been written to detect and count the heartbeat and also to calculate the calories burnt. © 2015 IEEE.


Reddy G.K.,G Pulla Reddy Engineering College
Proceedings of 2015 IEEE 9th International Conference on Intelligent Systems and Control, ISCO 2015 | Year: 2015

With increasing contribution of leakage in total active power, run-time leakage control techniques are becoming extremely important. The Pass-Transistor Logic (PTL) is a better way to implement circuits designed for low power applications. As the technology is growing pass transistor logic has gained the prominent importance. In this design of 1 bit ALU, PTL technology has been deliberately implemented. The Boolean equations have been modified in order to reduce the transistor count, and also reuse of hardware has also been achieved. © 2015 IEEE.


Sunanda P.,G Pulla Reddy Engineering College | Vineela A.,G Pulla Reddy Engineering College
2015 Conference on Power, Control, Communication and Computational Technologies for Sustainable Growth, PCCCTSG 2015 | Year: 2015

In today's world there is a tremendous increase in the number of users using the Internet. As a result the e-commerce websites have been emerging to encourage the users of Internet. But these e-commerce websites are facing the problem in recommending the items to the users. In view of this challenge, an Agglomerative Hierarchical Clustering for Hybrid Recommender Systems approach is proposed in this paper which aims at recruiting similar items in the same clusters to recommend items which are similar both at content as well as at rating. Technically, this approach can be performed in two stages. In the first stage, the available items are divided into small-scale clusters, for further processing. And in the second stage, Hybrid Recommender Systems algorithm is imposed on one of the clusters. As the number of the items in a cluster is much less than the total number of the item available on the web, it is expected that the online execution time of Hybrid Recommender Systems can be reduced. At last, to verify the availability of this approach several experiments are conducted. © 2015 IEEE.


Reddy G.K.,G Pulla Reddy Engineering College | Rao D.S.B.,G Pulla Reddy Engineering College
Proceedings of 2015 IEEE 9th International Conference on Intelligent Systems and Control, ISCO 2015 | Year: 2015

Adders are the basic building blocks of any processor or data path application. In adder design carry generation is the critical path. To reduce the power consumption of data path we need to reduce Area and number of transistors of the adder. Carry Select Adder is one of the fast adder used in many data path applications. In this paper Power consumption, area and delay of different carry select adders for 8bit, 16bit, 32bit, 64bit have been examined. A detailed comparative analysis has been done in Area, delay and power to all the Carry select adders. A new design based on D latch has reduced area, power And delay as compared with the regular SQRT CSLA. Power, delay and area have been calculated by using SYNOPSYS Design Vision tool. The results analysis shows that the new D latch based carry save adder CSLA structure is better than the regular SQRT CSLA. © 2015 IEEE.


Sravani E.,G Pulla Reddy Engineering College | Reddy N.R.S.,G Pulla Reddy Engineering College
IEEE International Conference on Computer Communication and Control, IC4 2015 | Year: 2015

Multilevel inverter is very effective in reducing the harmonics of AC waveform and useful for high power applications. Compared to the conventional two level inverters, it has many advantages such as higher dc link voltages, low electromagnetic interference and reduced harmonic distortion. But, it has some disadvantages such as usage of more switches, voltage balancing problem and complex pulse width modulation control. Overcoming these disadvantages, in this paper a new multilevel inverter topology with reversing voltage component to improve the overall performance is proposed. The proposed topology requires less number of switches and carrier signals compared to other topologies. Hence the overall cost and complexity of the circuit is reduced especially for higher output levels. The performance of a nine level proposed topology has been analyzed in terms of total harmonic distortion (THD) by using MATLAB/Simulink. © 2015 IEEE.


Urmila B.,G Pulla Reddy Engineering College | Subba Rayudu D.,Brindavan Institute of Technology and science
Journal of Engineering and Applied Sciences | Year: 2011

A Three-Level Voltage Source Inverter is used increasingly to supply a variable frequency and variable voltage for variable speed applications. A suitable pulse width modulation technique is employed to obtain the required output voltage at the line side of the inverter. This paper studies popular multi-level topology, Diode Clamped or Neutral Point Clamped for three-level. Two methods of Sine-triangle and two methods of Space Vector Pulse Width Modulation are employed to generate the modulation wave. These modulation waves are compared against a triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves used in SPWM. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. Space Vector Modulation Technique has become the important PWM technique for three phase Voltage Source Inverters because of its increased dc bus utilization and reduced harmonic distortion compared to SPWM. The four PWM methods are simulated in MATLAB/SIMULINK software and are compared for THD and Capacitor Balance. Programs are carried out using Embedded Editor functions and Matlab editor functions. The simulation study reveals that Space vector PWM utilizes dc bus voltage more effectively, generates less THD and improved capacitor balance when compared to Sine PWM. © 2006-2011 Asian Research Publishing Network (ARPN).


Devendra M.,G Pulla Reddy Engineering College | Manjunathachari K.,University of Hyderabad
International Conference on Signal Processing and Communication Engineering Systems - Proceedings of SPACES 2015, in Association with IEEE | Year: 2015

Very accurate estimation of the signal direction of arrival (DOA) has received a tremendous interest in communication and radar systems for commercial and as well as for military applications. This paper proposes the implementation of finding direction of arrival of the signal to an array system using MUSIC (Multiple Signal Classification) algorithm. The solution includes finding general Eigen values and used Jacobi algorithm for the calculation of Eigen values and Eigen vectors, which uses rotation mode to realize Eigen value decomposition in order to reduce computations and finally achieves real time array direction finding. Performance estimation of music algorithm by varying number of antenna elements in an array is performed and Simulation results are obtained using MATLAB. © 2015 IEEE.

Loading G Pulla Reddy Engineering College collaborators
Loading G Pulla Reddy Engineering College collaborators