Tokyo, Japan
Tokyo, Japan

Fuji Electric Co., Ltd. , operating under the brand name FE, is a Japanese holding company that retains manufacturing companies of pressure transmitters, flowmeters, gas analyzers, controllers, inverters, pumps, generators, ICs, motors, and power equipment. Wikipedia.

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Patent
Fuji Electric Co. | Date: 2017-01-27

A reference voltage generation circuit includes a voltage dividing circuit, a transistor, and a capacitor. The voltage dividing circuit divides a power-supply voltage into a specified level to generate a predetermined voltage. The transistor has a gate applied with the predetermined voltage and a drain outputting, as a reference voltage, a voltage obtained by adding the predetermined voltage and a threshold voltage of the transistor. The capacitor bypasses the gate and source of the transistor. Moreover, one end of the capacitor is connected to the gate of the transistor, and the other end of the capacitor is connected to the source of the transistor and ground. Furthermore, an electric charge output source which outputs an electric charge is connected to the drain of the transistor.


Patent
Fuji Electric Co. | Date: 2016-09-30

A semiconductor module includes case that houses a semiconductor device therein and a fastener that is connected at one end thereof to the case. The fastener includes a first extending portion that is connected at one end hereof to the case and extends away from the case, and a second extending portion that is connected at one end thereof to the first extending portion and extends toward the case, where the second extending portion has a variable angle with respect to the first extending portion depending on an external force. The second extending portion has a through hole penetrating through the second extending portion from a front surface of the second extending portion to a back surface of the second extending portion; and a projection that is provided on the back surface of the second extending portion, the projection being positioned closer to the case than the through hole is.


Patent
Fuji Electric Co. | Date: 2016-09-28

A terminal pressing frame of a semiconductor device is disposed so as to form a first gap partially from the bottom surface of an L-shaped leg portion of an external terminal and a second gap from an inside surface of a resin case. Adhesive spreads to the second gap and further spreads to the first gap connected to the second gap, consequent to the pressure when a metal base is assembled. The spreading of the adhesive to the first gap fixes an L-shaped leg portion of the external terminal and the terminal pressing frame to each other; and the spreading of adhesive to the second gap fixes the resin case and the terminal pressing frame to each other.


Patent
Fuji Electric Co. | Date: 2017-01-26

A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type.


A recombination center is formed within the bandgap of at least a silicon carbide material used to form an n^( )drift layer in a SiC-MOSFET. This recombination center is an impurity level formed by doping the n^( )drift layer with boron (B) or the like and/or a defect level constituted by defects formed by irradiating the n^( )drift layer with an electron beam. Due to the presence of this recombination center, the effective bandgap E_(g1 )of the silicon carbide material of the n^( )drift layer is set to be narrower than the original bandgap E_(g0 )and less than the valence band offset E_(V0 )of a silicon carbide/insulating film interface. As a result, the photon energy created by recombination of electrons and holes while a body diode of the SiC-MOSFET is conducting current in a forward direction is less than the valence band offset E_(V0 )of the silicon carbide/insulating film interface.


Patent
Fuji Electric Co. | Date: 2017-01-26

A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.


Patent
Fuji Electric Co. | Date: 2017-01-30

A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.


Provided is an electrophotographic photoreceptor 1 including the outer periphery of a cylindrical substrate 20, at least a photosensitive layer 21. One or more processed lines 20a are provided on one or both of end portions in the axial direction outside an image forming region of the outer peripheral surface of the substrate 20 along the circumferential direction. Also provided is an image forming apparatus including the electrophotographic photoreceptor.


Patent
Fuji Electric Co. | Date: 2016-10-12

With a semiconductor device fabrication method, an oxide film and a thermal oxide film formed over a semiconductor substrate are etched and ions are implanted in the semiconductor substrate in a high-temperature environment with the etched oxide film as a mask. Furthermore, the thermal oxide film has high adhesion to the semiconductor substrate. As a result, even if a difference in linear expansion coefficient arises between the semiconductor substrate and the oxide film due to a change in the linear expansion coefficient of the semiconductor substrate, the oxide film does not peel off the semiconductor substrate or crack because the oxide film is formed over the semiconductor substrate with the thermal oxide film therebetween.


Patent
Fuji Electric Co. | Date: 2016-11-04

A banknote processing device includes: a plurality of storage units configured to store a banknote having a predetermined condition in a storage unit corresponding to the banknote among the plurality of storage units when the banknote is fed through a depositing port provided on a device main body; and a dispensing box configured to discharge the banknote through a dispensing port provided on the dispensing box by conveying the banknote, which is sent from the storage unit, to the dispensing box when a dispensing instruction is given. The dispensing box is configured to collect the banknote being stored in the storage units when a collecting instruction is given.

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