Fresscale Semiconductor Malaysia SDN BHD

Petaling Jaya, Malaysia

Fresscale Semiconductor Malaysia SDN BHD

Petaling Jaya, Malaysia

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Kid W.B.,University of Tenaga Nasional | Leng E.P.,Fresscale Semiconductor Malaysia SDN BHD | Yong C.C.,Fresscale Semiconductor Malaysia SDN BHD | Yi O.X.,University of Tenaga Nasional | Kar Y.B.,University of Tenaga Nasional
2011 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2011 - Programme and Abstracts | Year: 2011

Gold wires are commonly used for wire-bonding and it fits well the industrial requirements. However, the price of Gold wires increasing significantly, Copper wires is a potential replacement for Gold due to their superior electrical and mechanical properties. In order to incorporate Cu in the wire-bonding process, substantial data regarding aging and intermetallic formation of Cu-Al bonds is required and the results are compared with Au samples. In this study, the bond integrity and thermal aging of Cu-Al and Au-Al wire-bonds were investigated. The Copper and Gold wire-bonds samples were heat-treated at temperature of 225°C for 4.5, 13.5, 26, 52 and 97 hours respectively. The intermetallics of the wire-bonds, and in particular the Al-Cu interface, were studied. Discontinuous and non-uniform of Cu-Al intermetallics regions were found in the thermal aging samples. The thickness of Cu-Al intermetallics is growing linearly with the temperature as the diffusion rate increases in higher temperature. The Cu-Al bond is weak compare to Au-Al in accordance with aging through wire pull test. © 2011 IEEE.


Kid W.B.,University of Tenaga Nasional | Leng E.P.,Fresscale Semiconductor Malaysia SDN BHD | Seong L.B.,Fresscale Semiconductor Malaysia SDN BHD | Weily C.,University of Tenaga Nasional | Kar Y.B.,University of Tenaga Nasional
2011 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2011 - Programme and Abstracts | Year: 2011

Nowadays, increasing of gold price and decreasing of dielectric let copper and low-k dielectric materials become a new technology and are increasingly chosen as preferred interconnect insulated material in semiconductor applications. In this paper, a C45 ultra low k wafer technology with bond-over-active bond pads, on a thermally enhanced BGA package with 3131mm large body size is selected to study. Aluminum wire type, bonding capillary, and wire bonding parameters, were selected as critical factors in this study. Both were used for bonding parameters optimization. Critical responses such as ball size, ball height/bonded ball diameter ratio, wire pull strength, ball shear strength, and wire peel strength were studied to understand the wire bonding effect of C45 ultra low k and 40m pad pitch. Analysis between copper and gold wire were performed for comparison purpose at different thermal aging read point. The thermal aging read point were studied at 175°C for 168, 504 and 1008 hours while at temperature of 225°C for 4.5, 13.5, 26, 52 and 97 hours respectively. This is used to study the IMC thickness of Cu-Al. To investigate the effects of IMC formation on the copper wire on Al pad, wire pull, wire peel and ball shear test has to be construct. © 2011 IEEE.


Leong H.,University of Tenaga Nasional | Yap B.,University of Tenaga Nasional | Khan N.,Fresscale Semiconductor Malaysia SDN BHD | Ibrahim M.R.,Fresscale Semiconductor Malaysia SDN BHD | Tan L.C.,Fresscale Semiconductor Malaysia SDN BHD
Microelectronics Reliability | Year: 2014

Insulated Cu wire technology has immense potential for fine pitch wire bonding interconnection. Understanding the behavior of the insulated Cu free air ball (FAB) formation is crucial for wire bonding process. The FAB formation, size, shape and cleanliness under different conditions for 20 μm insulated Cu wire were investigated using SEM, FESEM and FTIR surface analysis. The results were compared with that of bare Cu wire. Consistently spherical residue free FAB of insulated Cu wire were formed using forming gas. The samples with insulated Cu wire consistently produced larger FAB than that of bare Cu wire, indicating that the energy required for free air ball formation is lower. Basic bonding performances in terms of ball bond strength, intermetallic (IMC) coverage growth and stitch bond strength of insulated Cu wire at time zero are also discussed in the paper. © 2014 Elsevier Ltd. All rights.


Hungyang L.,University of Tenaga Nasional | Boonkar Y.,University of Tenaga Nasional | Yong T.C.,University of Malaya | Khan N.,Fresscale Semiconductor Malaysia SDN BHD | And 2 more authors.
Proceedings of the 16th Electronics Packaging Technology Conference, EPTC 2014 | Year: 2014

Today, microelectronics devices are getting smaller with more I/Os. Conventional ultra fine pitch wire bonding is facing wire-to wire short and wire sweeping issues. The use of insulated Cu wire is a potential technology enabling greater wire density, and wires touching and crossing, as the wire is coated with a layer or organic coating to prevent wire-to-wire short. In this paper we analyze the reliability of insulated Cu wire with diameter of 20 μm in PBGA package under unbiased HAST, TC and HTS reliability stressing using standard, touched wires profile and extreme loop height without kinks profile. Ball shear, wire pull and stitch pull tests as well as Cu/Al IMC thickness measurement test w performed after reliability stressing for bare Cu and insulated Cu wire samples. Results show that insulated Cu wire reliability samples show similar ball bond strength performance after the ball shear and wire pull test. Although stitch pull strength of insulated Cu is ∼17% less than bare Cu samples, the reliability results indicate that insulated Cu stitch bond has good reliability. Effect of the capillary touchdowns to the ball and stitch bond integrity of bare Cu and insulated Cu wire bonding is also presented in this paper. Capillary residue build up on the tip surface was investigated. We found capillary condition and life are comparable to bare Cu wire capillary. © 2014 IEEE.


Wong B.K.,University of Tenaga Nasional | Yong C.C.,Fresscale Semiconductor Malaysia SDN BHD | Eu P.L.,Fresscale Semiconductor Malaysia SDN BHD | Yap B.K.,University of Tenaga Nasional
International Conference on Electronic Devices, Systems, and Applications | Year: 2011

With SiO2 dielectric under aluminum pads, a 60 m bond pad pitch with 52 um bond pad opening Cu wire bonding process was developed in PBGA Hip 7 PGE wafer technology. The critical factors (wire type, capillary, and bonding parameter) and critical responses (bonded ball diameter, bonded ball height, wire pull, ball shear and number of metal lift/peeling and ball lift after wire pull) are affecting bonding quality. Design of experiment and response of surface were used to optimize the bonding parameters. The wire pull and ball shear test at three thermal aging read points were studied. © 2011 IEEE.


Leong H.Y.,University of Tenaga Nasional | Yap B.K.,University of Tenaga Nasional | Khan N.,Fresscale Semiconductor Malaysia SDN BHD | Ibrahim M.R.,Fresscale Semiconductor Malaysia SDN BHD | And 2 more authors.
Materials Research Innovations | Year: 2014

Insulated Cu wire technology offers potential solutions for fine and ultra-fine pitch wire bonding as the insulator coating on the bare wire prevents wires shorting problem. Most previous works focused on insulated wire stitch bonding. This paper presents a comparison study between insulated Cu and bare Cu wire ball-bonding process characterisation in the standpoints of free air ball formation, Al splash, hardness, ball bond strength and intermetallic growth at the bond interface study. Spherical and clean free air ball was formed using lower electric flame off energy compared to bare Cu wire. The study shows that insulated Cu bonding demonstrated comparable equivalent ball bond strength to bare Cu wire bonding at T0 and even after subjected to isothermal aging 175°C up to 1008 hours. Intermetallic formation was uniform at the bond interface for both wires. Insulated Cu wire demonstrates good bondability and reliability performance, suitable for fine pitch wire bonding in large-scale integration applications. © 2014 W. S. Maney & Son Ltd.


Leong H.Y.,University of Tenaga Nasional | Mohd F.Z.,Fresscale Semiconductor Malaysia SDN BHD | Ibrahim M.R.,Fresscale Semiconductor Malaysia SDN BHD | Kid W.B.,Fresscale Semiconductor Malaysia SDN BHD | And 3 more authors.
Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium | Year: 2012

Insulated Cu wire is the next generation technology in fine pitch and high density wire bonding, which enables wire crossing and touching without concern for wire-to-wire shorts. However, insulated Cu wire bonding is still at the infant stage compared to Cu wire bonding. This study investigates the wire bond process in term of free air ball (FAB) and ball formation using 20μm Cu wire and insulated Cu wire with target bonded ball size about 35μm. Insulated Cu wire needs a different set of EFO setting compared to Cu wire. Spherical and residue free FAB of insulated Cu was able to form with forming gas. With a set electric flame off (EFO) setting, insulated Cu FAB consistently larger than Cu FAB. The experimental results show clearly that the energy required for the FAB formation for insulated Cu wire is ∼20% lower than the Cu wire, probably due to the lesser heat loss from the wire during the EFO firing. Key bonding parameters for insulated Cu were EFO current, EFO time, bond power and bond force to meet the required ball size. This study shows that insulated Cu wire requires less demanding ball bond parameters than Cu wire, indicating softer ball which could be favorable for the sensitive bond structures. Bonding strength in term of ball shear and wire pull strength between the insulated Cu wire and Cu wire is very similar. Other key responses such as Al remnant, pad cratering and intermetallic compound have been studied and will be discussed in details in the paper. Our research successfully established good wire bonding process conditions for the insulated Cu wire and subsequently demonstrated that the technology is feasible using presently available wire bonder. © 2012 IEEE.


Aziz A.A.,Fresscale Semiconductor Malaysia SDN BHD | Danaher F.,Fresscale Semiconductor Malaysia SDN BHD
Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium | Year: 2015

Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment. © 2014 IEEE.


Aziz A.A.,Fresscale Semiconductor Malaysia SDN BHD | Danaher F.,Fresscale Semiconductor Malaysia SDN BHD | Hashim A.,Fresscale Semiconductor Malaysia SDN BHD
Proceedings of the 16th Electronics Packaging Technology Conference, EPTC 2014 | Year: 2014

Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment. © 2014 IEEE.

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