Gif - sur - Yvette, France

French Atomic Energy Commission

www.cea.fr
Gif - sur - Yvette, France

The Commissariat à l'énergie atomique et aux énergies alternatives or CEA, is a French public government-funded research organisation in the areas of energy, defense and security, information technologies and health technologies. The CEA maintains a cross-disciplinary culture of engineers and researchers, building on the synergies between fundamental and technological research Wikipedia.


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An electrochemically actuatable electronic component comprises: a substrate; at least one first and one second actuating electrodes; at least one first and one second measuring electrodes; at least one storing electrode configured to free ions under the action of the actuating electrodes; at least one ionic conductor able to conduct the ions and that is located in a region placed between the measuring electrodes; a device suitable for: applying a voltage or a current between the first and second actuating electrodes to allow the migration of ions from the storing electrode to the first actuating electrode forming thereon an electrochemical deposition through the ionic conductor and for measuring, between the first and second measuring electrodes, a modification of at least one characteristic of the region placed between the first and second measuring electrodes, to determine at least one characteristic of the electronic component.


Method of making a transistor with semiconducting nanowires, including:


Patent
French Atomic Energy Commission | Date: 2016-11-10

A method for manufacturing a PCRAM memory includes forming in a first dielectric layer arranged on a substrate, which includes bottom electrodes, a first rectilinear trench opening onto the set of electrodes; depositing a first active layer in the first trench, such that the first active layer is in electrical contact with the electrodes; covering the first active layer with a second dielectric layer; etching, in the second and second dielectric layers and the first active layer, additional rectilinear trenches oriented perpendicularly to the first trench, to obtain a group of memory devices each including a portion of the first active layer in electrical contact with one of the electrodes; filling the additional trenches with a sacrificial dielectric material; performing an anisotropic etching of the sacrificial material to expose a side surface of each portion of the first active layer; and covering the side surface with a second active layer.


Patent
French Atomic Energy Commission | Date: 2016-11-15

An electrochemical cell includes a membrane electrode assembly and a bipolar plate. The membrane electrode assembly includes a proton exchange membrane and first and second electrodes. The bipolar plate includes conductive sheets, coolant flow channels are made between the conductive sheets. An outer face of a conductive sheet includes reactant flow channels and a first rib extending on the side of the reactant flow channels. A gasket extends on the first rib. The bipolar plate includes an intermediate zone extending between the first rib and the first electrode, a first band in which the sheets have complementary shapes nested one in the other over the entire length of a coolant flow channel, and a second band in which a sheet includes reliefs in contact with the membrane electrode assembly.


Patent
Ulis and French Atomic Energy Commission | Date: 2017-01-06

A method of manufacturing a detector capable of detecting a wavelength range [_(8); _(14)] centered on a wavelength _(10), including: forming said device on a substrate by depositing a sacrificial layer totally embedding said device; forming, on the sacrificial layer, a cap including first, second, and third optical structures transparent in said range [_(8); _(14)], the second and third optical structures having equivalent refraction indexes at wavelength _(10 )respectively greater than or equal to 3.4 and smaller than or equal to 2.3; forming a vent of access to the sacrificial layer through a portion of the cap, and then applying, through the vent, an etching to totally remove the sacrificial layer.


Patent
French Atomic Energy Commission | Date: 2017-01-18

There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.


Patent
French Atomic Energy Commission | Date: 2017-01-18

A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.


This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm^(2); being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10^(3 )g/m^(2)/day.


Patent
French Atomic Energy Commission | Date: 2017-02-03

A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*10^(16 )cm^(3 )and at most equal to 2*10^(18 )cm^(3), the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.


Patent
French Atomic Energy Commission | Date: 2017-02-03

A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.

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