Toulouse, France

Freescale Semiconductor

www.freescale.com
Toulouse, France

Freescale Semiconductor, Inc. is an American multinational corporation headquartered in Austin, Texas with design, research and development, manufacturing and sales operations in more than 75 locations in 19 countries. The company employs 17,000 people worldwide.Freescale designs and produces embedded hardware and software for the automotive, networking, industrial and consumer markets with a current emphasis on technology enablement of the Internet of Things , Software-Defined Networking and Advanced Driver Assistance Systems .Freescale’s product portfolio includes microcontrollers , microprocessors , digital signal processors, digital signal controllers, sensors, RF power integrated circuits and power management ICs. The company also offers software development tools to support product design and development. Freescale’s current patent portfolio includes approximately 6,100 patent families.Freescale currently ranks 8th among semiconductor companies in the United States and is ranked 16th worldwide, as measured by total revenue. 17 billion Freescale semiconductor products are in use around the world today, enabling applications such as vehicle networking and information, vehicle radar and vision systems, networking security appliances, network routers and switches, hospital and in-home healthcare devices, smart energy, factory automation, eReaders and wearable devices. Wikipedia.

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A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.


Patent
Freescale Semiconductor | Date: 2015-11-12

A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.


A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. The memory access engine tracks history of a requested segment by updating the working frame unit when the requested segment in the workspace is modified by the executing task.


Patent
Freescale Semiconductor | Date: 2016-09-04

Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.


An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.


Patent
Freescale Semiconductor | Date: 2015-11-16

A MEMS device includes a mass system capable of undergoing oscillatory drive motion along a drive axis and oscillatory sense motion along a sense axis perpendicular to the drive axis. A quadrature correction unit includes a fixed electrode and a movable electrode coupled to the movable mass system, each being lengthwise oriented along the drive axis. The movable electrode is spaced apart from the fixed electrode by a gap having an initial width. At least one of the fixed and movable electrodes includes an extrusion region extending toward the other of the fixed and movable electrodes. The movable electrode undergoes oscillatory motion with the mass system such that the extrusion region is periodically spaced apart from the other of the fixed and movable electrodes by a gap exhibiting a second width that is less than the first width thereby enabling capacitance enhancement between the electrodes.


Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.


Patent
Freescale Semiconductor | Date: 2016-07-03

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.


Patent
Freescale Semiconductor | Date: 2016-08-11

A non-volatile memory (NVM) system has a main NVM sector with multiple memory segments, a redundant NVM sector for storing recovery records, an address-matching circuit having multiple memory sections, each adapted to store a pair of main and substitute addresses, and an NVM controller. The NVM controller is configured to determine if a first memory segment of the main NVM sector is no longer usable and, consequently (i) create a recovery record for storage in the redundant NVM sector that includes the address of the first memory segment and the data associated with the first memory segment, and (ii) add a pair of main and substitute addresses to the address-matching circuit, where the main address is the address of the first memory segment and the substitute address identifies a substitute location for the data associated with the first memory segment.


Patent
Freescale Semiconductor | Date: 2016-10-28

One embodiment of making a diode includes forming a first electrode to which an electric field is applied; forming a second electrode to which the electric field is applied; and forming a vapor gap region between the first electrode and the second electrode. A total capacitance measured between the first electrode and the second electrode varies based on presence of a polar vapor species on at least a portion of an electrode surface of at least one of the first electrode and the second electrode.

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