Toulouse, France
Toulouse, France

Freescale Semiconductor, Inc. is an American multinational corporation headquartered in Austin, Texas with design, research and development, manufacturing and sales operations in more than 75 locations in 19 countries. The company employs 17,000 people worldwide.Freescale designs and produces embedded hardware and software for the automotive, networking, industrial and consumer markets with a current emphasis on technology enablement of the Internet of Things , Software-Defined Networking and Advanced Driver Assistance Systems .Freescale’s product portfolio includes microcontrollers , microprocessors , digital signal processors, digital signal controllers, sensors, RF power integrated circuits and power management ICs. The company also offers software development tools to support product design and development. Freescale’s current patent portfolio includes approximately 6,100 patent families.Freescale currently ranks 8th among semiconductor companies in the United States and is ranked 16th worldwide, as measured by total revenue. 17 billion Freescale semiconductor products are in use around the world today, enabling applications such as vehicle networking and information, vehicle radar and vision systems, networking security appliances, network routers and switches, hospital and in-home healthcare devices, smart energy, factory automation, eReaders and wearable devices. Wikipedia.


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Patent
Freescale Semiconductor | Date: 2016-09-04

Electromagnetic compatibility (EMC) of a system-on-a-chip (SoC) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a SoC) from a controller to an embedded nonvolatile memory (NVM). The error-detection code used causes an EMC event to introduce errors into the transmitted codewords with relatively high probability. In response to an error being detected in the transmitted codeword, a set of safeguarding operations are performed to prevent the data stored in the NVM from being uncontrollably changed.


A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.


Patent
Freescale Semiconductor | Date: 2016-09-04

An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.


Patent
Freescale Semiconductor | Date: 2016-09-04

A single-inductor DC-DC converter generates two DC output voltages at two capacitors. The converter selectively transfers energy from a battery to the inductor or from the inductor to a selected capacitor. While the converter is still settling, the converter is regulated based on only the more deficient DC output voltage. After the converter has already settled, the converter is regulated based on the common-mode voltage for both DC output voltages. By regulating the still-settling converter based on only the more deficient DC output voltage, instead of the common-mode voltage, even greater deficiencies in that already more-deficient DC output voltage are avoided.


Patent
Freescale Semiconductor | Date: 2016-06-03

A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.


Patent
Freescale Semiconductor | Date: 2016-04-19

A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and the inside. Inside the package, a bidirectional vertical power transistor is present with a controllable bidirectional current path, through a body of the bidirectional vertical power transistor, between a first current terminal of the bidirectional vertical power transistor connected to the first current pin and a second current terminal of the bidirectional vertical power transistor connected to the second current pin. A control circuit connects the control pin to the body terminal and the control terminal to drive the body and the control terminal, which allows current through the body in a forward direction, from the first current terminal to the second terminal, as a function of the control voltage, and to block current in a reverse direction regardless of the voltage.


Patent
Freescale Semiconductor | Date: 2016-09-04

A method for conserving power in a computing device having a volatile system memory, a non-volatile storage device, and a processor executing an operating system and including an internal non-volatile memory (NVM). The method includes receiving, at the processor, a request to enter the computing device into a hibernation mode, suspending, by the processor, execution of the operating system, copying, by the processor, substantially the entire contents of the volatile system memory into the non-volatile storage device, storing, in the internal NVM of the processor, a hibernate flag, and turning off power to the computing device.


Patent
Freescale Semiconductor | Date: 2016-09-04

A method for conserving power in a computing device including a processor connected to an volatile system memory and having a processing core, always-on non-wakeup (AONW) resources, and a system memory controller, includes receiving a request at the processor to enter a low power state retention mode, saving, in the volatile system memory, control register settings for each of the AONW resources, placing the volatile system memory in a self-refresh mode to maintain all data stored in the volatile system memory, placing the system memory controller in a low power state, and turning off power to the processing core and all of the AONW resources.


A processing device includes a target processor instruction memory to store a plurality of memory access instructions, and a compiler. A vector invariant candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector invariant access code, and in response: the complier to generate first replacement code that vectorizes the memory access instruction using vector invariant access code, and to replace the memory access instruction with the first replacement code. A vector modulo addressing candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector modulo addressing access code, and in response: the complier to generate second replacement code that vectorizes the memory access instruction using vector modulo addressing code, and to replace the memory access instruction with the second replacement code.


Patent
Freescale Semiconductor | Date: 2016-02-17

Adaptive message caches are disclosed for packet replay and/or flood protection in mesh network devices. The adaptive message cache includes a replay protection area (RPA) and a flood protection area (FPA). For each received packet, a packet security processor compares packet metadata to metadata entries stored for prior packets within the RPA to provide a replay protection check. If a replay protection check is not passed, the packet is dropped. If passed, the packet security processor compares the packet metadata to metadata entries stored for prior packets within the FPA to provide a flood protection check. If the flood protection check is not passed, the packet is dropped. If passed, the received packet is authenticated for the mesh network. Entries within the RPA/FPA are then updated using the packet metadata. Further, the sizes of the RPA and FPA can be adaptively adjusted based upon the packet metadata.

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