Time filter

Source Type

Paskaleva A.,Bulgarian Academy of Science | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Bauer A.J.,Fraunhofer Institute for Integrated Systems and Device Technology | Lemberger M.,Fraunhofer Institute for Integrated Systems and Device Technology | And 2 more authors.
Materials Science in Semiconductor Processing

The influence of oxidation pulse during atomic layer deposition (ALD) process on electrical and dielectric properties of metal-insulator-metal (MIM) structures with different ZrO2- based (e.g. pure ZrO2, Al- and Si- doped ZrO2) high-k dielectrics and different thicknesses has been investigated. Strongly pulse-time dependent as well as independent phenomena are observed and their thorough analysis has given more insight on the processes taking place in these structures thus allowing further optimization of their electrical performance. Longer oxidation pulses produce films with larger thicknesses which may be related to the incorporation of excess oxygen in the layers and the formation of less dense films. Incorporation of Al and 10 s pulse time are the most beneficial and provide structures with the lowest leakage current. At high positive voltages a significant increase of current and a change of I-V curve shape with increasing pulse time have been observed. The possible processes which provoke this change have been discussed. The analysis of leakage current mechanisms reveals that neither incorporation of Al or Si in ZrO2 nor oxidation pulse time change the energy position of traps participating in the conduction process, hence the nature of these traps remains unaffected - it is a single positively charged oxygen vacancy in ZrO2. The oxidation pulse time of 5-10 s is the optimal one which provides structures fulfilling the requirements for next generation MIM-based dynamic random access memories (DRAMs). © 2014 Elsevier Ltd. All rights reserved. Source

Jegert G.,TU Munich | Popescu D.,TU Munich | Lugli P.,TU Munich | Haufel M.J.,University of Zurich | And 2 more authors.
Physical Review B - Condensed Matter and Materials Physics

We assess the impact of structural relaxation of defects upon charging on trap-assisted tunneling in high-κ dielectric materials. ZrO 2/Al 2O 3/ZrO2 thin films are taken as an exemplary system. In our completely different approach, a first-principles defect model is derived from Hedins GW approximation calculations, which is then coupled to kinetic Monte Carlo charge transport simulations. Comparison between simulation and experiment demonstrates that it is often imperative to take structural relaxation processes into account when modeling nanoscale transport across defect states. © 2012 American Physical Society. Source

Jegert G.,TU Munich | Kersch A.,Munich University of Applied Sciences | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Schroder U.,NaMLab gGmbH | Lugli P.,TU Munich
Applied Physics Letters

We report on a simulation algorithm, based on kinetic Monte Carlo techniques, that allows us to investigate transport through high-permittivity dielectrics. In the example of TiN/ ZrO2 /TiN capacitor structures, using best-estimate physical parameters, we have identified the dominant transport mechanisms. Comparison with experimental data reveals the transport to be dominated by Poole-Frenkel emission from donorlike trap states at low fields and trap-assisted tunneling at high fields. © 2010 American Institute of Physics. Source

Neuner J.,Fraunhofer Center Nanoelectronic Technology | Zienert I.,AMD Inc | Peeva A.,AMD Inc | Preusse A.,AMD Inc | And 2 more authors.
Microelectronic Engineering

Downscaling of copper interconnects is demanding more knowledge about the microstructure and grain growth mechanisms in sub 100 nm dimensions. Large grains are needed to reduce the resistivity and to increase the reliability of narrow lines. Plating additives are used for a void free filling of the interconnecting vias and lines. Fractions of these additives are incorporated into the copper as impurities during electrochemical deposition. In the present paper the role of additive concentration on grain growth is investigated. Interconnect lines from 72 nm to 1.9 μm line width were completely filled with copper using different additive concentrations in the electrolyte. The impurity level was measured by time of flight secondary ion mass spectrometry. The samples were stored at room-temperature to achieve self-annealing or tempered at low and high temperatures. Self-annealing slows down with increasing additive concentration whereas bamboo-like grains are present after annealing all samples at high temperatures. Grain growth was studied as well as the average grain size, resistivity, and {1 1 1} texture. © 2009 Elsevier B.V. All rights reserved. Source

Flachowsky S.,FH Dresden | Illgen R.,FH Dresden | Herrmann T.,FH Dresden | Klix W.,FH Dresden | And 6 more authors.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p -metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n -MOSFET is embedded silicon-carbon (eSi:C). However, n -MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20 nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels. © 2010 American Vacuum Society. Source

Discover hidden collaborations