Fraunhofer Center Nanoelectronic Technology

Dresden, Germany

Fraunhofer Center Nanoelectronic Technology

Dresden, Germany
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Paskaleva A.,Bulgarian Academy of Science | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Bauer A.J.,Fraunhofer Institute for Integrated Systems and Device Technology | Lemberger M.,Fraunhofer Institute for Integrated Systems and Device Technology | And 2 more authors.
Materials Science in Semiconductor Processing | Year: 2015

The influence of oxidation pulse during atomic layer deposition (ALD) process on electrical and dielectric properties of metal-insulator-metal (MIM) structures with different ZrO2- based (e.g. pure ZrO2, Al- and Si- doped ZrO2) high-k dielectrics and different thicknesses has been investigated. Strongly pulse-time dependent as well as independent phenomena are observed and their thorough analysis has given more insight on the processes taking place in these structures thus allowing further optimization of their electrical performance. Longer oxidation pulses produce films with larger thicknesses which may be related to the incorporation of excess oxygen in the layers and the formation of less dense films. Incorporation of Al and 10 s pulse time are the most beneficial and provide structures with the lowest leakage current. At high positive voltages a significant increase of current and a change of I-V curve shape with increasing pulse time have been observed. The possible processes which provoke this change have been discussed. The analysis of leakage current mechanisms reveals that neither incorporation of Al or Si in ZrO2 nor oxidation pulse time change the energy position of traps participating in the conduction process, hence the nature of these traps remains unaffected - it is a single positively charged oxygen vacancy in ZrO2. The oxidation pulse time of 5-10 s is the optimal one which provides structures fulfilling the requirements for next generation MIM-based dynamic random access memories (DRAMs). © 2014 Elsevier Ltd. All rights reserved.

Kuligk A.,TU Braunschweig | Nguyen C.D.,Globalfoundries | Lohr D.-A.,Fraunhofer Center Nanoelectronic Technology | Beyer V.,Fraunhofer Center Nanoelectronic Technology | Meinerzhagen B.,TU Braunschweig
ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day' | Year: 2013

Program disturb may ultimately limit the scalability of modern NAND flash memory technologies and is typically most serious for the memory cells neighboring the string select transistors. The feasibility, accuracy, and predictive capability of a new advanced physical simulation model for the program disturb in NAND flash memories is demonstrated by means of a comprehensive experimental verification based on a 48 nm TANOS technology. For the first time it is demonstrated that the dependence of program disturb on the distance between the memory cells and the select transistors can be accurately modeled by a physical model without fitting any model parameter. © 2013 IEEE.

Beug M.F.,Physikalisch - Technische Bundesanstalt | Melde T.,Nanoelectronic Materials Laboratory GmbH | Czernohorsky M.,Fraunhofer Center Nanoelectronic Technology | Hoffmann R.,Fraunhofer Center Nanoelectronic Technology | And 3 more authors.
IEEE Transactions on Electron Devices | Year: 2010

In this paper, we investigate the specific impact of an additional silicon oxide layer (sealing oxide) on top of the charge-trap nitride on the electrical performance of small-dimension and large TANOS charge-trapping (CT) memory cells. We observe a significant improvement in charge retention on both our target 48-nm nand TANOS cells and on large 5 μm long and wide memory cells. However, erase performance is partially degraded by this additional silicon dioxide top-dielectric layer. The presented intrinsic CT stack retention for 3.5-nm sealing oxide, which is visible on large cell structures, clearly shows the potential for multilevel cell operation.We further identified trapping in the Al2O3 states of the blocking dielectric to improve the program and erase performance of conventional TANOS memory cells. However, detrapping from these trap states was found to be the root cause of insufficient retention. © 2006 IEEE.

Flachowsky S.,FH Dresden | Illgen R.,FH Dresden | Herrmann T.,FH Dresden | Klix W.,FH Dresden | And 6 more authors.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures | Year: 2010

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p -metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n -MOSFET is embedded silicon-carbon (eSi:C). However, n -MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20 nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels. © 2010 American Vacuum Society.

Jegert G.,TU Munich | Popescu D.,TU Munich | Lugli P.,TU Munich | Haufel M.J.,University of Zürich | And 2 more authors.
Physical Review B - Condensed Matter and Materials Physics | Year: 2012

We assess the impact of structural relaxation of defects upon charging on trap-assisted tunneling in high-κ dielectric materials. ZrO 2/Al 2O 3/ZrO2 thin films are taken as an exemplary system. In our completely different approach, a first-principles defect model is derived from Hedins GW approximation calculations, which is then coupled to kinetic Monte Carlo charge transport simulations. Comparison between simulation and experiment demonstrates that it is often imperative to take structural relaxation processes into account when modeling nanoscale transport across defect states. © 2012 American Physical Society.

Lanza M.,University of Barcelona | Porti M.,University of Barcelona | Nafra M.,University of Barcelona | Aymerich X.,University of Barcelona | And 7 more authors.
IEEE Transactions on Nanotechnology | Year: 2011

In this paper, atomic force microscopy-based techniques have been used to study, at nanoscale, the dependence of the electrical properties of Al 2O3 stacks for flash memories on the annealing temperature (TA). The electrical characterization has been combined with other techniques (for example, transmission electron microscopy) that have allowed to investigate the dependence of the stack crystallization and the Si diffusion from the substrate to the gate oxide on TA. The combination of both the analyses has allowed to explore if there is a relation between the percentage of diffused silicon and material crystallization with the conductivity and charge trapping of Al2O3 stacks. © 2006 IEEE.

Jegert G.,TU Munich | Kersch A.,Munich University of Applied Sciences | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Lugli P.,TU Munich
IEEE Transactions on Electron Devices | Year: 2011

Leakage currents in TiN-κ-ZrO2/TiNcapacitors were simulated by using a novel kinetic Monte Carlo algorithm specially designed to describe tunneling transport of charge carriers in high-κ dielectrics, including defect-assisted transport mechanisms. Comparing simulation results with experimental data, a model for electronic transport was established and validated. Transport was found to be dominated by PooleFrenkel emission from positively charged bulk trap states at medium voltages and trap-assisted tunneling at high voltages. Information on the conduction band offset at the TiN/ZrO2 interface as well as on the trap depth was extracted. The model accurately describes the scaling of the leakage current with temperature and with thickness of the dielectric film, and it provides insight into the mutual interdependence of the competing transport mechanisms. © 2006 IEEE.

Jegert G.,TU Munich | Kersch A.,Munich University of Applied Sciences | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Lugli P.,TU Munich
Journal of Applied Physics | Year: 2011

In this paper, we investigate the influence of electrode roughness on the leakage current in TiN/high-κ ZrO2/TiN (TZT) thin-film capacitors which are used in dynamic random access memory cells. Based on a microscopic transport model, which is expanded to incorporate electrode roughness, we assess the ultimate scaling potential of TZT capacitors in terms of equivalent oxide thickness, film smoothness, thickness fluctuations, defect density and distribution, and conduction band offset (CBO). The model is based on three-dimensional, fully self-consistent, kinetic Monte Carlo transport simulations. Tunneling transport in the bandgap of the dielectric is treated, which includes defect-assisted transport mechanisms. Electrode roughness is described in the framework of fractal geometry. While the short-range roughness of the electrodes is found not to influence significantly the leakage current, thickness fluctuations of the dielectric have a major impact. For thinner dielectric films they cause a transformation of the dominant transport mechanism from Poole-Frenkel conduction to trap-assisted tunneling. Consequently, the sensitivity of the leakage current on electrode roughness drastically increases on downscaling. Based on the simulations, optimization of the CBO is suggested as the most viable strategy to extend the scalability of TZT capacitors over the next chip generations. © 2011 American Institute of Physics.

Jegert G.,TU Munich | Kersch A.,Munich University of Applied Sciences | Weinreich W.,Fraunhofer Center Nanoelectronic Technology | Schroder U.,NaMLab gGmbH | Lugli P.,TU Munich
Applied Physics Letters | Year: 2010

We report on a simulation algorithm, based on kinetic Monte Carlo techniques, that allows us to investigate transport through high-permittivity dielectrics. In the example of TiN/ ZrO2 /TiN capacitor structures, using best-estimate physical parameters, we have identified the dominant transport mechanisms. Comparison with experimental data reveals the transport to be dominated by Poole-Frenkel emission from donorlike trap states at low fields and trap-assisted tunneling at high fields. © 2010 American Institute of Physics.

Neuner J.,Fraunhofer Center Nanoelectronic Technology | Zienert I.,AMD Inc | Peeva A.,AMD Inc | Preusse A.,AMD Inc | And 2 more authors.
Microelectronic Engineering | Year: 2010

Downscaling of copper interconnects is demanding more knowledge about the microstructure and grain growth mechanisms in sub 100 nm dimensions. Large grains are needed to reduce the resistivity and to increase the reliability of narrow lines. Plating additives are used for a void free filling of the interconnecting vias and lines. Fractions of these additives are incorporated into the copper as impurities during electrochemical deposition. In the present paper the role of additive concentration on grain growth is investigated. Interconnect lines from 72 nm to 1.9 μm line width were completely filled with copper using different additive concentrations in the electrolyte. The impurity level was measured by time of flight secondary ion mass spectrometry. The samples were stored at room-temperature to achieve self-annealing or tempered at low and high temperatures. Self-annealing slows down with increasing additive concentration whereas bamboo-like grains are present after annealing all samples at high temperatures. Grain growth was studied as well as the average grain size, resistivity, and {1 1 1} texture. © 2009 Elsevier B.V. All rights reserved.

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