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Turki M.,Habib Mehrez | Marrakchi Z.,FLEXRAS Technologies | Abid M.,University of Sfax
Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 | Year: 2013

Hardware prototyping is becoming increasingly important in the system on chip design cycle. It allows a fast hardware verification within the time to market constraints before reaching the manufacturing phase. © 2013 IEEE. Source


Pangracious V.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies | Amouri E.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments. © 2013 Springer-Verlag. Source


Parvez H.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies | Kilic A.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie
ACM Transactions on Reconfigurable Technology and Systems | Year: 2011

This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) [Parvez et al. 2009]. An ASIF can be considered as an FPGA with reduced flexibility, or as a reconfigurable ASIC that can implement a set of application circuits which will operate at mutually exclusive times. Execution of different application circuits can be switched by loading their respective bitstream on an ASIF. An ASIF that is reduced from a heterogeneous FPGA is termed as a heterogeneous ASIF. It is shown that a standard-cell-based heterogeneous ASIF for a set of 10 opencore application circuits is 9.6 times smaller than a single-driver mesh-based heterogeneous FPGA. The area gap between ASIC and ASIF is not too significant; however, it can be reduced by designing repeatedly used components of ASIF in full-custom. Unlike an ASIC, an ASIF is a reprogrammable device that can be used to reprogram new or modified circuits at a limited scale. © 2011 ACM. Source


Farooq U.,University Pierre and Marie Curie | Parvez H.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies
International Journal of Reconfigurable Computing | Year: 2011

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results. Copyright © 2011 Umer Farooq et al. Source


Farooq U.,University Pierre and Marie Curie | Parvez H.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies
Microprocessors and Microsystems | Year: 2012

A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF. © 2012 Elsevier B.V. All rights reserved. Source

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