Saint-Léger-du-Bourg-Denis, France
Saint-Léger-du-Bourg-Denis, France

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Turki M.,Habib Mehrez | Marrakchi Z.,FlexRAS Technologies | Abid M.,University of Sfax
Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 | Year: 2013

Hardware prototyping is becoming increasingly important in the system on chip design cycle. It allows a fast hardware verification within the time to market constraints before reaching the manufacturing phase. © 2013 IEEE.


Pangracious V.,University Pierre and Marie Curie | Marrakchi Z.,Flexras Technologies | Amouri E.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments. © 2013 Springer-Verlag.


Farooq U.,University Pierre and Marie Curie | Parvez H.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies
International Journal of Reconfigurable Computing | Year: 2011

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results. Copyright © 2011 Umer Farooq et al.


Tang Q.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Tuna M.,Flexras Technologies
Proceedings - 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014 | Year: 2014

We can classify multi-FPGA prototyping platforms in three categories: hardwired off-the-shelf, cabling and custom. Three points are developed in this paper. Firstly, an automatic design flow is proposed to generate a cabling platform and a custom platform for a given design. Then, the optimal width of cables for a cabling multi-FPGA platform is explored. Finally, the performances of these three multi-FPGA platforms are compared. The results show that the cabling platform achieves up to 82% gain in performance, and the custom platform achieves up to 100%, compared to the hardwired off-the-shelf platform. The custom platform achieves up to 20% gain in performance over the cabling platform. Therefore the results show that, apart from some stringent constraints (such as deployment cost or specific frequency needed), the relatively new cabling paradigm with the proposed automatic, inter-FPGA tracks distribution tool, offers an attractive alternative compared to the two other platforms. © 2014 IEEE.


Parvez H.,University Pierre and Marie Curie | Marrakchi Z.,Flexras Technologies | Kilic A.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie
ACM Transactions on Reconfigurable Technology and Systems | Year: 2011

This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) [Parvez et al. 2009]. An ASIF can be considered as an FPGA with reduced flexibility, or as a reconfigurable ASIC that can implement a set of application circuits which will operate at mutually exclusive times. Execution of different application circuits can be switched by loading their respective bitstream on an ASIF. An ASIF that is reduced from a heterogeneous FPGA is termed as a heterogeneous ASIF. It is shown that a standard-cell-based heterogeneous ASIF for a set of 10 opencore application circuits is 9.6 times smaller than a single-driver mesh-based heterogeneous FPGA. The area gap between ASIC and ASIF is not too significant; however, it can be reduced by designing repeatedly used components of ASIF in full-custom. Unlike an ASIC, an ASIF is a reprogrammable device that can be used to reprogram new or modified circuits at a limited scale. © 2011 ACM.


Tang Q.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Tuna M.,Flexras Technologies
Proceedings of the 2013 International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2013 | Year: 2013

Multi-FPGA boards suffer from large timing delays in inter-FPGA physical tracks compared to intra-FPGA track delays, as well as a limited bandwidth between FPGAs due to the limited number of I/Os per FPGA. In order to tackle this problem, an algorithm which routes multi-terminal nets in multi-point tracks is proposed in this paper to spare FPGA I/Os. Experiments are conducted using Gaisler Research Benchmarks. Firstly, each testbench will be implemented in an off-the-shelf board. The results show that the system frequency can be increased in the off-the-shelf board by the proposed routing algorithm. Secondly, an automatic design flow which generates a custom multi-FPGA board is enhanced by generating multi-point tracks in the board, and each testbench will be implemented with the proposed routing algorithm in custom boards. The results show that the system frequency is improved in the custom board with both 2- and multi-point tracks. © 2013 IEEE.


Farooq U.,University Pierre and Marie Curie | Parvez H.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Marrakchi Z.,FLEXRAS Technologies
Microprocessors and Microsystems | Year: 2012

A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF. © 2012 Elsevier B.V. All rights reserved.


Tang Q.,University Pierre and Marie Curie | Mehrez H.,University Pierre and Marie Curie | Tuna M.,Flexras Technologies
Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP | Year: 2012

Reaching a physical limitation in terms of power consumption, the new chosen axis to increase the performance is to scale the number of processing elements (PEs) instead of increasing the speed of processors. These complex systems often take the form of a Multi-Core System-on-Chip (MCSoC) in which individual nodes are connected using a Network-on-Chip (NoC). FPGA-based prototyping is no longer optional to test these very large designs. A multi-FPGA prototyping board, which is a collection of FPGAs, is used when the logic capacity of a single FPGA is insufficient. Nevertheless, multi-FPGA boards come with some constraints, which lower the system frequency. However, cluster-based MCSoCs have a great value: their flexibility in terms of form factor. In this paper, a parameterizable clusterbased MCSoC with a mesh topology has been designed. An indicator based on the average Rent's Rule of cluster-based MCSoCs has been proposed to predict the best form factor in order to obtain the maximum prototyping system frequency. The targeted prototyping platform is a six Virtex-5 multi-FPGA board. The results show that for a given total number of PEs in cluster-based MCSoCs, a lower indicator can result in a higher system frequency. ©2012 IEEE.


Patent
Flexras Technologies | Date: 2013-05-24

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of: partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; and the number of crossings of programmable chips of a critical combinatorial path; establishing a routing of the signals between programmable chips using the physical resources available.


Trademark
Flexras Technologies | Date: 2012-11-20

Apparatus for recording, transmitting, reproducing or processing sound or images; cash registers, calculating machines, data processing equipment and computers; computer game programs; recorded computer aided design software for designing electronic systems, printed circuit boards and integrated circuits; recorded computer aided design software for simulating and testing designs of electronic systems, printed circuit boards and integrated circuits; recorded computer software for creating, managing, and deploying cloud computing infrastructure services; recorded computer software for high-speed processing and storage of data using multiple CPUs; recorded computer aided design software for designing field-programmable gate array circuits (FPGAs); recorded computer aided design software for designing complex programmable logic devices (CPLDs); recorded computer aided design software for building system on a chip (SoC) and system on a programmable chip (SoPC; recorded computer aided design software for use in the fields of integrated circuit (IC) emulation and rapid prototyping machines and platforms; computer peripheral devices; integrated circuit cards.

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